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![Mario Limonciello](/assets/img/avatar_default.png)
Setting the century forward has been failing on AMD platforms.
There was a previous attempt at fixing this for family 0x17 as part of
commit 7ad295d519
("rtc: Fix the AltCentury value on AMD/Hygon
platform") but this was later reverted due to some problems reported
that appeared to stem from an FW bug on a family 0x17 desktop system.
The same comments mentioned in the previous commit continue to apply
to the newer platforms as well.
```
MC146818 driver use function mc146818_set_time() to set register
RTC_FREQ_SELECT(RTC_REG_A)'s bit4-bit6 field which means divider stage
reset value on Intel platform to 0x7.
While AMD/Hygon RTC_REG_A(0Ah)'s bit4 is defined as DV0 [Reference]:
DV0 = 0 selects Bank 0, DV0 = 1 selects Bank 1. Bit5-bit6 is defined
as reserved.
DV0 is set to 1, it will select Bank 1, which will disable AltCentury
register(0x32) access. As UEFI pass acpi_gbl_FADT.century 0x32
(AltCentury), the CMOS write will be failed on code:
CMOS_WRITE(century, acpi_gbl_FADT.century).
Correct RTC_REG_A bank select bit(DV0) to 0 on AMD/Hygon CPUs, it will
enable AltCentury(0x32) register writing and finally setup century as
expected.
```
However in closer examination the change previously submitted was also
modifying bits 5 & 6 which are declared reserved in the AMD documentation.
So instead modify just the DV0 bank selection bit.
Being cognizant that there was a failure reported before, split the code
change out to a static function that can also be used for exclusions if
any regressions such as Mikhail's pop up again.
Cc: Jinke Fan <fanjinke@hygon.cn>
Cc: Mikhail Gavrilov <mikhail.v.gavrilov@gmail.com>
Link: https://lore.kernel.org/all/CABXGCsMLob0DC25JS8wwAYydnDoHBSoMh2_YLPfqm3TTvDE-Zw@mail.gmail.com/
Link: https://www.amd.com/system/files/TechDocs/51192_Bolton_FCH_RRG.pdf
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Link: https://lore.kernel.org/r/20220111225750.1699-1-mario.limonciello@amd.com
290 lines
7 KiB
C
290 lines
7 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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#include <linux/bcd.h>
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#include <linux/delay.h>
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#include <linux/export.h>
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#include <linux/mc146818rtc.h>
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#ifdef CONFIG_ACPI
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#include <linux/acpi.h>
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#endif
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/*
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* Execute a function while the UIP (Update-in-progress) bit of the RTC is
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* unset.
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*
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* Warning: callback may be executed more then once.
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*/
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bool mc146818_avoid_UIP(void (*callback)(unsigned char seconds, void *param),
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void *param)
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{
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int i;
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unsigned long flags;
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unsigned char seconds;
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for (i = 0; i < 10; i++) {
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spin_lock_irqsave(&rtc_lock, flags);
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/*
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* Check whether there is an update in progress during which the
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* readout is unspecified. The maximum update time is ~2ms. Poll
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* every msec for completion.
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*
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* Store the second value before checking UIP so a long lasting
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* NMI which happens to hit after the UIP check cannot make
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* an update cycle invisible.
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*/
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seconds = CMOS_READ(RTC_SECONDS);
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if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP) {
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spin_unlock_irqrestore(&rtc_lock, flags);
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mdelay(1);
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continue;
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}
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/* Revalidate the above readout */
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if (seconds != CMOS_READ(RTC_SECONDS)) {
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spin_unlock_irqrestore(&rtc_lock, flags);
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continue;
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}
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if (callback)
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callback(seconds, param);
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/*
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* Check for the UIP bit again. If it is set now then
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* the above values may contain garbage.
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*/
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if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP) {
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spin_unlock_irqrestore(&rtc_lock, flags);
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mdelay(1);
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continue;
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}
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/*
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* A NMI might have interrupted the above sequence so check
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* whether the seconds value has changed which indicates that
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* the NMI took longer than the UIP bit was set. Unlikely, but
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* possible and there is also virt...
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*/
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if (seconds != CMOS_READ(RTC_SECONDS)) {
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spin_unlock_irqrestore(&rtc_lock, flags);
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continue;
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}
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spin_unlock_irqrestore(&rtc_lock, flags);
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return true;
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}
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return false;
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}
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EXPORT_SYMBOL_GPL(mc146818_avoid_UIP);
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/*
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* If the UIP (Update-in-progress) bit of the RTC is set for more then
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* 10ms, the RTC is apparently broken or not present.
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*/
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bool mc146818_does_rtc_work(void)
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{
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return mc146818_avoid_UIP(NULL, NULL);
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}
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EXPORT_SYMBOL_GPL(mc146818_does_rtc_work);
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struct mc146818_get_time_callback_param {
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struct rtc_time *time;
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unsigned char ctrl;
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#ifdef CONFIG_ACPI
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unsigned char century;
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#endif
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#ifdef CONFIG_MACH_DECSTATION
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unsigned int real_year;
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#endif
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};
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static void mc146818_get_time_callback(unsigned char seconds, void *param_in)
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{
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struct mc146818_get_time_callback_param *p = param_in;
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/*
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* Only the values that we read from the RTC are set. We leave
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* tm_wday, tm_yday and tm_isdst untouched. Even though the
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* RTC has RTC_DAY_OF_WEEK, we ignore it, as it is only updated
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* by the RTC when initially set to a non-zero value.
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*/
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p->time->tm_sec = seconds;
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p->time->tm_min = CMOS_READ(RTC_MINUTES);
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p->time->tm_hour = CMOS_READ(RTC_HOURS);
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p->time->tm_mday = CMOS_READ(RTC_DAY_OF_MONTH);
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p->time->tm_mon = CMOS_READ(RTC_MONTH);
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p->time->tm_year = CMOS_READ(RTC_YEAR);
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#ifdef CONFIG_MACH_DECSTATION
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p->real_year = CMOS_READ(RTC_DEC_YEAR);
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#endif
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#ifdef CONFIG_ACPI
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if (acpi_gbl_FADT.header.revision >= FADT2_REVISION_ID &&
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acpi_gbl_FADT.century) {
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p->century = CMOS_READ(acpi_gbl_FADT.century);
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} else {
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p->century = 0;
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}
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#endif
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p->ctrl = CMOS_READ(RTC_CONTROL);
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}
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int mc146818_get_time(struct rtc_time *time)
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{
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struct mc146818_get_time_callback_param p = {
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.time = time
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};
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if (!mc146818_avoid_UIP(mc146818_get_time_callback, &p)) {
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memset(time, 0, sizeof(*time));
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return -EIO;
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}
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if (!(p.ctrl & RTC_DM_BINARY) || RTC_ALWAYS_BCD)
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{
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time->tm_sec = bcd2bin(time->tm_sec);
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time->tm_min = bcd2bin(time->tm_min);
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time->tm_hour = bcd2bin(time->tm_hour);
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time->tm_mday = bcd2bin(time->tm_mday);
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time->tm_mon = bcd2bin(time->tm_mon);
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time->tm_year = bcd2bin(time->tm_year);
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#ifdef CONFIG_ACPI
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p.century = bcd2bin(p.century);
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#endif
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}
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#ifdef CONFIG_MACH_DECSTATION
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time->tm_year += p.real_year - 72;
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#endif
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#ifdef CONFIG_ACPI
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if (p.century > 19)
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time->tm_year += (p.century - 19) * 100;
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#endif
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/*
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* Account for differences between how the RTC uses the values
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* and how they are defined in a struct rtc_time;
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*/
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if (time->tm_year <= 69)
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time->tm_year += 100;
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time->tm_mon--;
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return 0;
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}
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EXPORT_SYMBOL_GPL(mc146818_get_time);
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/* AMD systems don't allow access to AltCentury with DV1 */
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static bool apply_amd_register_a_behavior(void)
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{
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#ifdef CONFIG_X86
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if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
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boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
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return true;
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#endif
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return false;
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}
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/* Set the current date and time in the real time clock. */
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int mc146818_set_time(struct rtc_time *time)
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{
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unsigned long flags;
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unsigned char mon, day, hrs, min, sec;
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unsigned char save_control, save_freq_select;
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unsigned int yrs;
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#ifdef CONFIG_MACH_DECSTATION
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unsigned int real_yrs, leap_yr;
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#endif
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unsigned char century = 0;
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yrs = time->tm_year;
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mon = time->tm_mon + 1; /* tm_mon starts at zero */
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day = time->tm_mday;
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hrs = time->tm_hour;
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min = time->tm_min;
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sec = time->tm_sec;
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if (yrs > 255) /* They are unsigned */
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return -EINVAL;
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#ifdef CONFIG_MACH_DECSTATION
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real_yrs = yrs;
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leap_yr = ((!((yrs + 1900) % 4) && ((yrs + 1900) % 100)) ||
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!((yrs + 1900) % 400));
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yrs = 72;
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/*
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* We want to keep the year set to 73 until March
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* for non-leap years, so that Feb, 29th is handled
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* correctly.
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*/
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if (!leap_yr && mon < 3) {
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real_yrs--;
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yrs = 73;
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}
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#endif
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#ifdef CONFIG_ACPI
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if (acpi_gbl_FADT.header.revision >= FADT2_REVISION_ID &&
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acpi_gbl_FADT.century) {
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century = (yrs + 1900) / 100;
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yrs %= 100;
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}
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#endif
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/* These limits and adjustments are independent of
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* whether the chip is in binary mode or not.
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*/
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if (yrs > 169)
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return -EINVAL;
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if (yrs >= 100)
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yrs -= 100;
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spin_lock_irqsave(&rtc_lock, flags);
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save_control = CMOS_READ(RTC_CONTROL);
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spin_unlock_irqrestore(&rtc_lock, flags);
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if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
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sec = bin2bcd(sec);
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min = bin2bcd(min);
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hrs = bin2bcd(hrs);
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day = bin2bcd(day);
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mon = bin2bcd(mon);
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yrs = bin2bcd(yrs);
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century = bin2bcd(century);
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}
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spin_lock_irqsave(&rtc_lock, flags);
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save_control = CMOS_READ(RTC_CONTROL);
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CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL);
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save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
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if (apply_amd_register_a_behavior())
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CMOS_WRITE((save_freq_select & ~RTC_AMD_BANK_SELECT), RTC_FREQ_SELECT);
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else
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CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT);
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#ifdef CONFIG_MACH_DECSTATION
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CMOS_WRITE(real_yrs, RTC_DEC_YEAR);
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#endif
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CMOS_WRITE(yrs, RTC_YEAR);
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CMOS_WRITE(mon, RTC_MONTH);
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CMOS_WRITE(day, RTC_DAY_OF_MONTH);
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CMOS_WRITE(hrs, RTC_HOURS);
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CMOS_WRITE(min, RTC_MINUTES);
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CMOS_WRITE(sec, RTC_SECONDS);
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#ifdef CONFIG_ACPI
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if (acpi_gbl_FADT.header.revision >= FADT2_REVISION_ID &&
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acpi_gbl_FADT.century)
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CMOS_WRITE(century, acpi_gbl_FADT.century);
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#endif
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CMOS_WRITE(save_control, RTC_CONTROL);
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CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
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spin_unlock_irqrestore(&rtc_lock, flags);
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return 0;
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}
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EXPORT_SYMBOL_GPL(mc146818_set_time);
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