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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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![Alexandru Ardelean](/assets/img/avatar_default.png)
The 'delay_usecs' field was handled for backwards compatibility in case there were some users that still configured SPI delay transfers with this field. They should all be removed by now. Signed-off-by: Alexandru Ardelean <aardelean@deviqon.com> Link: https://lore.kernel.org/r/20210308145502.1075689-2-aardelean@deviqon.com Signed-off-by: Mark Brown <broonie@kernel.org>
597 lines
15 KiB
C
597 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* SPI-Engine SPI controller driver
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* Copyright 2015 Analog Devices Inc.
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* Author: Lars-Peter Clausen <lars@metafoo.de>
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*/
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#include <linux/clk.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/spi/spi.h>
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#define SPI_ENGINE_VERSION_MAJOR(x) ((x >> 16) & 0xff)
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#define SPI_ENGINE_VERSION_MINOR(x) ((x >> 8) & 0xff)
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#define SPI_ENGINE_VERSION_PATCH(x) (x & 0xff)
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#define SPI_ENGINE_REG_VERSION 0x00
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#define SPI_ENGINE_REG_RESET 0x40
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#define SPI_ENGINE_REG_INT_ENABLE 0x80
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#define SPI_ENGINE_REG_INT_PENDING 0x84
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#define SPI_ENGINE_REG_INT_SOURCE 0x88
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#define SPI_ENGINE_REG_SYNC_ID 0xc0
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#define SPI_ENGINE_REG_CMD_FIFO_ROOM 0xd0
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#define SPI_ENGINE_REG_SDO_FIFO_ROOM 0xd4
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#define SPI_ENGINE_REG_SDI_FIFO_LEVEL 0xd8
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#define SPI_ENGINE_REG_CMD_FIFO 0xe0
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#define SPI_ENGINE_REG_SDO_DATA_FIFO 0xe4
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#define SPI_ENGINE_REG_SDI_DATA_FIFO 0xe8
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#define SPI_ENGINE_REG_SDI_DATA_FIFO_PEEK 0xec
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#define SPI_ENGINE_INT_CMD_ALMOST_EMPTY BIT(0)
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#define SPI_ENGINE_INT_SDO_ALMOST_EMPTY BIT(1)
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#define SPI_ENGINE_INT_SDI_ALMOST_FULL BIT(2)
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#define SPI_ENGINE_INT_SYNC BIT(3)
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#define SPI_ENGINE_CONFIG_CPHA BIT(0)
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#define SPI_ENGINE_CONFIG_CPOL BIT(1)
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#define SPI_ENGINE_CONFIG_3WIRE BIT(2)
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#define SPI_ENGINE_INST_TRANSFER 0x0
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#define SPI_ENGINE_INST_ASSERT 0x1
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#define SPI_ENGINE_INST_WRITE 0x2
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#define SPI_ENGINE_INST_MISC 0x3
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#define SPI_ENGINE_CMD_REG_CLK_DIV 0x0
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#define SPI_ENGINE_CMD_REG_CONFIG 0x1
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#define SPI_ENGINE_MISC_SYNC 0x0
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#define SPI_ENGINE_MISC_SLEEP 0x1
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#define SPI_ENGINE_TRANSFER_WRITE 0x1
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#define SPI_ENGINE_TRANSFER_READ 0x2
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#define SPI_ENGINE_CMD(inst, arg1, arg2) \
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(((inst) << 12) | ((arg1) << 8) | (arg2))
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#define SPI_ENGINE_CMD_TRANSFER(flags, n) \
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SPI_ENGINE_CMD(SPI_ENGINE_INST_TRANSFER, (flags), (n))
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#define SPI_ENGINE_CMD_ASSERT(delay, cs) \
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SPI_ENGINE_CMD(SPI_ENGINE_INST_ASSERT, (delay), (cs))
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#define SPI_ENGINE_CMD_WRITE(reg, val) \
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SPI_ENGINE_CMD(SPI_ENGINE_INST_WRITE, (reg), (val))
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#define SPI_ENGINE_CMD_SLEEP(delay) \
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SPI_ENGINE_CMD(SPI_ENGINE_INST_MISC, SPI_ENGINE_MISC_SLEEP, (delay))
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#define SPI_ENGINE_CMD_SYNC(id) \
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SPI_ENGINE_CMD(SPI_ENGINE_INST_MISC, SPI_ENGINE_MISC_SYNC, (id))
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struct spi_engine_program {
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unsigned int length;
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uint16_t instructions[];
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};
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struct spi_engine {
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struct clk *clk;
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struct clk *ref_clk;
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spinlock_t lock;
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void __iomem *base;
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struct spi_message *msg;
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struct spi_engine_program *p;
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unsigned cmd_length;
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const uint16_t *cmd_buf;
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struct spi_transfer *tx_xfer;
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unsigned int tx_length;
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const uint8_t *tx_buf;
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struct spi_transfer *rx_xfer;
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unsigned int rx_length;
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uint8_t *rx_buf;
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unsigned int sync_id;
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unsigned int completed_id;
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unsigned int int_enable;
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};
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static void spi_engine_program_add_cmd(struct spi_engine_program *p,
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bool dry, uint16_t cmd)
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{
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if (!dry)
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p->instructions[p->length] = cmd;
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p->length++;
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}
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static unsigned int spi_engine_get_config(struct spi_device *spi)
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{
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unsigned int config = 0;
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if (spi->mode & SPI_CPOL)
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config |= SPI_ENGINE_CONFIG_CPOL;
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if (spi->mode & SPI_CPHA)
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config |= SPI_ENGINE_CONFIG_CPHA;
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if (spi->mode & SPI_3WIRE)
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config |= SPI_ENGINE_CONFIG_3WIRE;
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return config;
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}
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static unsigned int spi_engine_get_clk_div(struct spi_engine *spi_engine,
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struct spi_device *spi, struct spi_transfer *xfer)
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{
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unsigned int clk_div;
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clk_div = DIV_ROUND_UP(clk_get_rate(spi_engine->ref_clk),
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xfer->speed_hz * 2);
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if (clk_div > 255)
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clk_div = 255;
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else if (clk_div > 0)
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clk_div -= 1;
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return clk_div;
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}
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static void spi_engine_gen_xfer(struct spi_engine_program *p, bool dry,
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struct spi_transfer *xfer)
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{
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unsigned int len = xfer->len;
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while (len) {
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unsigned int n = min(len, 256U);
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unsigned int flags = 0;
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if (xfer->tx_buf)
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flags |= SPI_ENGINE_TRANSFER_WRITE;
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if (xfer->rx_buf)
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flags |= SPI_ENGINE_TRANSFER_READ;
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spi_engine_program_add_cmd(p, dry,
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SPI_ENGINE_CMD_TRANSFER(flags, n - 1));
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len -= n;
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}
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}
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static void spi_engine_gen_sleep(struct spi_engine_program *p, bool dry,
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struct spi_engine *spi_engine, unsigned int clk_div,
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struct spi_transfer *xfer)
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{
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unsigned int spi_clk = clk_get_rate(spi_engine->ref_clk);
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unsigned int t;
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int delay;
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delay = spi_delay_to_ns(&xfer->delay, xfer);
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if (delay < 0)
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return;
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delay /= 1000;
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if (delay == 0)
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return;
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t = DIV_ROUND_UP(delay * spi_clk, (clk_div + 1) * 2);
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while (t) {
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unsigned int n = min(t, 256U);
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spi_engine_program_add_cmd(p, dry, SPI_ENGINE_CMD_SLEEP(n - 1));
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t -= n;
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}
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}
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static void spi_engine_gen_cs(struct spi_engine_program *p, bool dry,
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struct spi_device *spi, bool assert)
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{
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unsigned int mask = 0xff;
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if (assert)
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mask ^= BIT(spi->chip_select);
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spi_engine_program_add_cmd(p, dry, SPI_ENGINE_CMD_ASSERT(1, mask));
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}
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static int spi_engine_compile_message(struct spi_engine *spi_engine,
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struct spi_message *msg, bool dry, struct spi_engine_program *p)
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{
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struct spi_device *spi = msg->spi;
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struct spi_transfer *xfer;
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int clk_div, new_clk_div;
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bool cs_change = true;
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clk_div = -1;
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spi_engine_program_add_cmd(p, dry,
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SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_CONFIG,
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spi_engine_get_config(spi)));
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list_for_each_entry(xfer, &msg->transfers, transfer_list) {
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new_clk_div = spi_engine_get_clk_div(spi_engine, spi, xfer);
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if (new_clk_div != clk_div) {
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clk_div = new_clk_div;
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spi_engine_program_add_cmd(p, dry,
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SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_CLK_DIV,
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clk_div));
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}
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if (cs_change)
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spi_engine_gen_cs(p, dry, spi, true);
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spi_engine_gen_xfer(p, dry, xfer);
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spi_engine_gen_sleep(p, dry, spi_engine, clk_div, xfer);
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cs_change = xfer->cs_change;
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if (list_is_last(&xfer->transfer_list, &msg->transfers))
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cs_change = !cs_change;
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if (cs_change)
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spi_engine_gen_cs(p, dry, spi, false);
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}
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return 0;
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}
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static void spi_engine_xfer_next(struct spi_engine *spi_engine,
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struct spi_transfer **_xfer)
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{
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struct spi_message *msg = spi_engine->msg;
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struct spi_transfer *xfer = *_xfer;
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if (!xfer) {
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xfer = list_first_entry(&msg->transfers,
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struct spi_transfer, transfer_list);
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} else if (list_is_last(&xfer->transfer_list, &msg->transfers)) {
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xfer = NULL;
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} else {
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xfer = list_next_entry(xfer, transfer_list);
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}
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*_xfer = xfer;
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}
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static void spi_engine_tx_next(struct spi_engine *spi_engine)
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{
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struct spi_transfer *xfer = spi_engine->tx_xfer;
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do {
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spi_engine_xfer_next(spi_engine, &xfer);
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} while (xfer && !xfer->tx_buf);
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spi_engine->tx_xfer = xfer;
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if (xfer) {
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spi_engine->tx_length = xfer->len;
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spi_engine->tx_buf = xfer->tx_buf;
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} else {
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spi_engine->tx_buf = NULL;
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}
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}
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static void spi_engine_rx_next(struct spi_engine *spi_engine)
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{
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struct spi_transfer *xfer = spi_engine->rx_xfer;
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do {
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spi_engine_xfer_next(spi_engine, &xfer);
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} while (xfer && !xfer->rx_buf);
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spi_engine->rx_xfer = xfer;
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if (xfer) {
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spi_engine->rx_length = xfer->len;
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spi_engine->rx_buf = xfer->rx_buf;
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} else {
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spi_engine->rx_buf = NULL;
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}
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}
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static bool spi_engine_write_cmd_fifo(struct spi_engine *spi_engine)
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{
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void __iomem *addr = spi_engine->base + SPI_ENGINE_REG_CMD_FIFO;
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unsigned int n, m, i;
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const uint16_t *buf;
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n = readl_relaxed(spi_engine->base + SPI_ENGINE_REG_CMD_FIFO_ROOM);
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while (n && spi_engine->cmd_length) {
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m = min(n, spi_engine->cmd_length);
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buf = spi_engine->cmd_buf;
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for (i = 0; i < m; i++)
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writel_relaxed(buf[i], addr);
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spi_engine->cmd_buf += m;
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spi_engine->cmd_length -= m;
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n -= m;
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}
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return spi_engine->cmd_length != 0;
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}
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static bool spi_engine_write_tx_fifo(struct spi_engine *spi_engine)
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{
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void __iomem *addr = spi_engine->base + SPI_ENGINE_REG_SDO_DATA_FIFO;
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unsigned int n, m, i;
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const uint8_t *buf;
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n = readl_relaxed(spi_engine->base + SPI_ENGINE_REG_SDO_FIFO_ROOM);
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while (n && spi_engine->tx_length) {
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m = min(n, spi_engine->tx_length);
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buf = spi_engine->tx_buf;
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for (i = 0; i < m; i++)
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writel_relaxed(buf[i], addr);
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spi_engine->tx_buf += m;
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spi_engine->tx_length -= m;
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n -= m;
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if (spi_engine->tx_length == 0)
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spi_engine_tx_next(spi_engine);
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}
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return spi_engine->tx_length != 0;
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}
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static bool spi_engine_read_rx_fifo(struct spi_engine *spi_engine)
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{
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void __iomem *addr = spi_engine->base + SPI_ENGINE_REG_SDI_DATA_FIFO;
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unsigned int n, m, i;
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uint8_t *buf;
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n = readl_relaxed(spi_engine->base + SPI_ENGINE_REG_SDI_FIFO_LEVEL);
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while (n && spi_engine->rx_length) {
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m = min(n, spi_engine->rx_length);
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buf = spi_engine->rx_buf;
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for (i = 0; i < m; i++)
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buf[i] = readl_relaxed(addr);
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spi_engine->rx_buf += m;
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spi_engine->rx_length -= m;
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n -= m;
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if (spi_engine->rx_length == 0)
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spi_engine_rx_next(spi_engine);
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}
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return spi_engine->rx_length != 0;
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}
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static irqreturn_t spi_engine_irq(int irq, void *devid)
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{
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struct spi_master *master = devid;
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struct spi_engine *spi_engine = spi_master_get_devdata(master);
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unsigned int disable_int = 0;
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unsigned int pending;
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pending = readl_relaxed(spi_engine->base + SPI_ENGINE_REG_INT_PENDING);
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if (pending & SPI_ENGINE_INT_SYNC) {
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writel_relaxed(SPI_ENGINE_INT_SYNC,
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spi_engine->base + SPI_ENGINE_REG_INT_PENDING);
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spi_engine->completed_id = readl_relaxed(
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spi_engine->base + SPI_ENGINE_REG_SYNC_ID);
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}
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spin_lock(&spi_engine->lock);
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if (pending & SPI_ENGINE_INT_CMD_ALMOST_EMPTY) {
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if (!spi_engine_write_cmd_fifo(spi_engine))
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disable_int |= SPI_ENGINE_INT_CMD_ALMOST_EMPTY;
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}
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if (pending & SPI_ENGINE_INT_SDO_ALMOST_EMPTY) {
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if (!spi_engine_write_tx_fifo(spi_engine))
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disable_int |= SPI_ENGINE_INT_SDO_ALMOST_EMPTY;
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}
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if (pending & (SPI_ENGINE_INT_SDI_ALMOST_FULL | SPI_ENGINE_INT_SYNC)) {
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if (!spi_engine_read_rx_fifo(spi_engine))
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disable_int |= SPI_ENGINE_INT_SDI_ALMOST_FULL;
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}
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if (pending & SPI_ENGINE_INT_SYNC) {
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if (spi_engine->msg &&
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spi_engine->completed_id == spi_engine->sync_id) {
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struct spi_message *msg = spi_engine->msg;
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kfree(spi_engine->p);
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msg->status = 0;
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msg->actual_length = msg->frame_length;
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spi_engine->msg = NULL;
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spi_finalize_current_message(master);
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disable_int |= SPI_ENGINE_INT_SYNC;
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}
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}
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if (disable_int) {
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spi_engine->int_enable &= ~disable_int;
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writel_relaxed(spi_engine->int_enable,
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spi_engine->base + SPI_ENGINE_REG_INT_ENABLE);
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}
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spin_unlock(&spi_engine->lock);
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return IRQ_HANDLED;
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}
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static int spi_engine_transfer_one_message(struct spi_master *master,
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struct spi_message *msg)
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{
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struct spi_engine_program p_dry, *p;
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struct spi_engine *spi_engine = spi_master_get_devdata(master);
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unsigned int int_enable = 0;
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unsigned long flags;
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size_t size;
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p_dry.length = 0;
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spi_engine_compile_message(spi_engine, msg, true, &p_dry);
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size = sizeof(*p->instructions) * (p_dry.length + 1);
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p = kzalloc(sizeof(*p) + size, GFP_KERNEL);
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if (!p)
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return -ENOMEM;
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spi_engine_compile_message(spi_engine, msg, false, p);
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spin_lock_irqsave(&spi_engine->lock, flags);
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spi_engine->sync_id = (spi_engine->sync_id + 1) & 0xff;
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spi_engine_program_add_cmd(p, false,
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SPI_ENGINE_CMD_SYNC(spi_engine->sync_id));
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spi_engine->msg = msg;
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spi_engine->p = p;
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spi_engine->cmd_buf = p->instructions;
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spi_engine->cmd_length = p->length;
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if (spi_engine_write_cmd_fifo(spi_engine))
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int_enable |= SPI_ENGINE_INT_CMD_ALMOST_EMPTY;
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spi_engine_tx_next(spi_engine);
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if (spi_engine_write_tx_fifo(spi_engine))
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int_enable |= SPI_ENGINE_INT_SDO_ALMOST_EMPTY;
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spi_engine_rx_next(spi_engine);
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if (spi_engine->rx_length != 0)
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int_enable |= SPI_ENGINE_INT_SDI_ALMOST_FULL;
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int_enable |= SPI_ENGINE_INT_SYNC;
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writel_relaxed(int_enable,
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spi_engine->base + SPI_ENGINE_REG_INT_ENABLE);
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spi_engine->int_enable = int_enable;
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spin_unlock_irqrestore(&spi_engine->lock, flags);
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return 0;
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}
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static int spi_engine_probe(struct platform_device *pdev)
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{
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struct spi_engine *spi_engine;
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struct spi_master *master;
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unsigned int version;
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int irq;
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int ret;
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irq = platform_get_irq(pdev, 0);
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if (irq <= 0)
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return -ENXIO;
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spi_engine = devm_kzalloc(&pdev->dev, sizeof(*spi_engine), GFP_KERNEL);
|
|
if (!spi_engine)
|
|
return -ENOMEM;
|
|
|
|
master = spi_alloc_master(&pdev->dev, 0);
|
|
if (!master)
|
|
return -ENOMEM;
|
|
|
|
spi_master_set_devdata(master, spi_engine);
|
|
|
|
spin_lock_init(&spi_engine->lock);
|
|
|
|
spi_engine->clk = devm_clk_get(&pdev->dev, "s_axi_aclk");
|
|
if (IS_ERR(spi_engine->clk)) {
|
|
ret = PTR_ERR(spi_engine->clk);
|
|
goto err_put_master;
|
|
}
|
|
|
|
spi_engine->ref_clk = devm_clk_get(&pdev->dev, "spi_clk");
|
|
if (IS_ERR(spi_engine->ref_clk)) {
|
|
ret = PTR_ERR(spi_engine->ref_clk);
|
|
goto err_put_master;
|
|
}
|
|
|
|
ret = clk_prepare_enable(spi_engine->clk);
|
|
if (ret)
|
|
goto err_put_master;
|
|
|
|
ret = clk_prepare_enable(spi_engine->ref_clk);
|
|
if (ret)
|
|
goto err_clk_disable;
|
|
|
|
spi_engine->base = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(spi_engine->base)) {
|
|
ret = PTR_ERR(spi_engine->base);
|
|
goto err_ref_clk_disable;
|
|
}
|
|
|
|
version = readl(spi_engine->base + SPI_ENGINE_REG_VERSION);
|
|
if (SPI_ENGINE_VERSION_MAJOR(version) != 1) {
|
|
dev_err(&pdev->dev, "Unsupported peripheral version %u.%u.%c\n",
|
|
SPI_ENGINE_VERSION_MAJOR(version),
|
|
SPI_ENGINE_VERSION_MINOR(version),
|
|
SPI_ENGINE_VERSION_PATCH(version));
|
|
ret = -ENODEV;
|
|
goto err_ref_clk_disable;
|
|
}
|
|
|
|
writel_relaxed(0x00, spi_engine->base + SPI_ENGINE_REG_RESET);
|
|
writel_relaxed(0xff, spi_engine->base + SPI_ENGINE_REG_INT_PENDING);
|
|
writel_relaxed(0x00, spi_engine->base + SPI_ENGINE_REG_INT_ENABLE);
|
|
|
|
ret = request_irq(irq, spi_engine_irq, 0, pdev->name, master);
|
|
if (ret)
|
|
goto err_ref_clk_disable;
|
|
|
|
master->dev.of_node = pdev->dev.of_node;
|
|
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_3WIRE;
|
|
master->bits_per_word_mask = SPI_BPW_MASK(8);
|
|
master->max_speed_hz = clk_get_rate(spi_engine->ref_clk) / 2;
|
|
master->transfer_one_message = spi_engine_transfer_one_message;
|
|
master->num_chipselect = 8;
|
|
|
|
ret = spi_register_master(master);
|
|
if (ret)
|
|
goto err_free_irq;
|
|
|
|
platform_set_drvdata(pdev, master);
|
|
|
|
return 0;
|
|
err_free_irq:
|
|
free_irq(irq, master);
|
|
err_ref_clk_disable:
|
|
clk_disable_unprepare(spi_engine->ref_clk);
|
|
err_clk_disable:
|
|
clk_disable_unprepare(spi_engine->clk);
|
|
err_put_master:
|
|
spi_master_put(master);
|
|
return ret;
|
|
}
|
|
|
|
static int spi_engine_remove(struct platform_device *pdev)
|
|
{
|
|
struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
|
|
struct spi_engine *spi_engine = spi_master_get_devdata(master);
|
|
int irq = platform_get_irq(pdev, 0);
|
|
|
|
spi_unregister_master(master);
|
|
|
|
free_irq(irq, master);
|
|
|
|
spi_master_put(master);
|
|
|
|
writel_relaxed(0xff, spi_engine->base + SPI_ENGINE_REG_INT_PENDING);
|
|
writel_relaxed(0x00, spi_engine->base + SPI_ENGINE_REG_INT_ENABLE);
|
|
writel_relaxed(0x01, spi_engine->base + SPI_ENGINE_REG_RESET);
|
|
|
|
clk_disable_unprepare(spi_engine->ref_clk);
|
|
clk_disable_unprepare(spi_engine->clk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id spi_engine_match_table[] = {
|
|
{ .compatible = "adi,axi-spi-engine-1.00.a" },
|
|
{ },
|
|
};
|
|
MODULE_DEVICE_TABLE(of, spi_engine_match_table);
|
|
|
|
static struct platform_driver spi_engine_driver = {
|
|
.probe = spi_engine_probe,
|
|
.remove = spi_engine_remove,
|
|
.driver = {
|
|
.name = "spi-engine",
|
|
.of_match_table = spi_engine_match_table,
|
|
},
|
|
};
|
|
module_platform_driver(spi_engine_driver);
|
|
|
|
MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
|
|
MODULE_DESCRIPTION("Analog Devices SPI engine peripheral driver");
|
|
MODULE_LICENSE("GPL");
|