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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-23 17:30:02 +00:00
![Matija Glavinic Pecotic](/assets/img/avatar_default.png)
Davinci needs to configure chipselect on transfer.
Fixes: 4a07b8bcd5
("spi: bitbang: Make chipselect callback optional")
Signed-off-by: Matija Glavinic Pecotic <matija.glavinic-pecotic.ext@nokia.com>
Reviewed-by: Alexander Sverdlin <alexander.sverdlin@nokia.com>
Link: https://lore.kernel.org/r/735fb7b0-82aa-5b9b-85e4-53f0c348cc0e@nokia.com
Signed-off-by: Mark Brown <broonie@kernel.org>
1053 lines
26 KiB
C
1053 lines
26 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2009 Texas Instruments.
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* Copyright (C) 2010 EF Johnson Technologies
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*/
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/gpio/consumer.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/platform_device.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/dmaengine.h>
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#include <linux/dma-mapping.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/spi_bitbang.h>
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#include <linux/slab.h>
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#include <linux/platform_data/spi-davinci.h>
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#define CS_DEFAULT 0xFF
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#define SPIFMT_PHASE_MASK BIT(16)
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#define SPIFMT_POLARITY_MASK BIT(17)
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#define SPIFMT_DISTIMER_MASK BIT(18)
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#define SPIFMT_SHIFTDIR_MASK BIT(20)
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#define SPIFMT_WAITENA_MASK BIT(21)
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#define SPIFMT_PARITYENA_MASK BIT(22)
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#define SPIFMT_ODD_PARITY_MASK BIT(23)
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#define SPIFMT_WDELAY_MASK 0x3f000000u
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#define SPIFMT_WDELAY_SHIFT 24
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#define SPIFMT_PRESCALE_SHIFT 8
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/* SPIPC0 */
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#define SPIPC0_DIFUN_MASK BIT(11) /* MISO */
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#define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */
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#define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */
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#define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */
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#define SPIINT_MASKALL 0x0101035F
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#define SPIINT_MASKINT 0x0000015F
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#define SPI_INTLVL_1 0x000001FF
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#define SPI_INTLVL_0 0x00000000
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/* SPIDAT1 (upper 16 bit defines) */
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#define SPIDAT1_CSHOLD_MASK BIT(12)
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#define SPIDAT1_WDEL BIT(10)
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/* SPIGCR1 */
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#define SPIGCR1_CLKMOD_MASK BIT(1)
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#define SPIGCR1_MASTER_MASK BIT(0)
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#define SPIGCR1_POWERDOWN_MASK BIT(8)
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#define SPIGCR1_LOOPBACK_MASK BIT(16)
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#define SPIGCR1_SPIENA_MASK BIT(24)
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/* SPIBUF */
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#define SPIBUF_TXFULL_MASK BIT(29)
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#define SPIBUF_RXEMPTY_MASK BIT(31)
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/* SPIDELAY */
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#define SPIDELAY_C2TDELAY_SHIFT 24
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#define SPIDELAY_C2TDELAY_MASK (0xFF << SPIDELAY_C2TDELAY_SHIFT)
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#define SPIDELAY_T2CDELAY_SHIFT 16
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#define SPIDELAY_T2CDELAY_MASK (0xFF << SPIDELAY_T2CDELAY_SHIFT)
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#define SPIDELAY_T2EDELAY_SHIFT 8
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#define SPIDELAY_T2EDELAY_MASK (0xFF << SPIDELAY_T2EDELAY_SHIFT)
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#define SPIDELAY_C2EDELAY_SHIFT 0
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#define SPIDELAY_C2EDELAY_MASK 0xFF
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/* Error Masks */
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#define SPIFLG_DLEN_ERR_MASK BIT(0)
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#define SPIFLG_TIMEOUT_MASK BIT(1)
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#define SPIFLG_PARERR_MASK BIT(2)
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#define SPIFLG_DESYNC_MASK BIT(3)
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#define SPIFLG_BITERR_MASK BIT(4)
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#define SPIFLG_OVRRUN_MASK BIT(6)
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#define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24)
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#define SPIFLG_ERROR_MASK (SPIFLG_DLEN_ERR_MASK \
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| SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \
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| SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \
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| SPIFLG_OVRRUN_MASK)
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#define SPIINT_DMA_REQ_EN BIT(16)
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/* SPI Controller registers */
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#define SPIGCR0 0x00
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#define SPIGCR1 0x04
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#define SPIINT 0x08
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#define SPILVL 0x0c
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#define SPIFLG 0x10
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#define SPIPC0 0x14
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#define SPIDAT1 0x3c
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#define SPIBUF 0x40
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#define SPIDELAY 0x48
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#define SPIDEF 0x4c
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#define SPIFMT0 0x50
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#define DMA_MIN_BYTES 16
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/* SPI Controller driver's private data. */
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struct davinci_spi {
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struct spi_bitbang bitbang;
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struct clk *clk;
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u8 version;
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resource_size_t pbase;
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void __iomem *base;
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u32 irq;
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struct completion done;
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const void *tx;
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void *rx;
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int rcount;
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int wcount;
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struct dma_chan *dma_rx;
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struct dma_chan *dma_tx;
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struct davinci_spi_platform_data pdata;
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void (*get_rx)(u32 rx_data, struct davinci_spi *);
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u32 (*get_tx)(struct davinci_spi *);
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u8 *bytes_per_word;
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u8 prescaler_limit;
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};
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static struct davinci_spi_config davinci_spi_default_cfg;
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static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *dspi)
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{
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if (dspi->rx) {
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u8 *rx = dspi->rx;
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*rx++ = (u8)data;
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dspi->rx = rx;
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}
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}
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static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *dspi)
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{
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if (dspi->rx) {
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u16 *rx = dspi->rx;
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*rx++ = (u16)data;
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dspi->rx = rx;
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}
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}
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static u32 davinci_spi_tx_buf_u8(struct davinci_spi *dspi)
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{
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u32 data = 0;
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if (dspi->tx) {
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const u8 *tx = dspi->tx;
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data = *tx++;
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dspi->tx = tx;
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}
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return data;
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}
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static u32 davinci_spi_tx_buf_u16(struct davinci_spi *dspi)
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{
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u32 data = 0;
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if (dspi->tx) {
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const u16 *tx = dspi->tx;
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data = *tx++;
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dspi->tx = tx;
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}
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return data;
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}
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static inline void set_io_bits(void __iomem *addr, u32 bits)
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{
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u32 v = ioread32(addr);
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v |= bits;
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iowrite32(v, addr);
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}
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static inline void clear_io_bits(void __iomem *addr, u32 bits)
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{
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u32 v = ioread32(addr);
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v &= ~bits;
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iowrite32(v, addr);
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}
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/*
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* Interface to control the chip select signal
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*/
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static void davinci_spi_chipselect(struct spi_device *spi, int value)
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{
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struct davinci_spi *dspi;
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struct davinci_spi_config *spicfg = spi->controller_data;
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u8 chip_sel = spi->chip_select;
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u16 spidat1 = CS_DEFAULT;
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dspi = spi_master_get_devdata(spi->master);
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/* program delay transfers if tx_delay is non zero */
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if (spicfg && spicfg->wdelay)
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spidat1 |= SPIDAT1_WDEL;
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/*
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* Board specific chip select logic decides the polarity and cs
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* line for the controller
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*/
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if (spi->cs_gpiod) {
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if (value == BITBANG_CS_ACTIVE)
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gpiod_set_value(spi->cs_gpiod, 1);
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else
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gpiod_set_value(spi->cs_gpiod, 0);
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} else {
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if (value == BITBANG_CS_ACTIVE) {
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if (!(spi->mode & SPI_CS_WORD))
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spidat1 |= SPIDAT1_CSHOLD_MASK;
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spidat1 &= ~(0x1 << chip_sel);
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}
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}
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iowrite16(spidat1, dspi->base + SPIDAT1 + 2);
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}
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/**
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* davinci_spi_get_prescale - Calculates the correct prescale value
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* @dspi: the controller data
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* @max_speed_hz: the maximum rate the SPI clock can run at
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*
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* This function calculates the prescale value that generates a clock rate
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* less than or equal to the specified maximum.
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*
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* Returns: calculated prescale value for easy programming into SPI registers
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* or negative error number if valid prescalar cannot be updated.
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*/
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static inline int davinci_spi_get_prescale(struct davinci_spi *dspi,
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u32 max_speed_hz)
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{
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int ret;
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/* Subtract 1 to match what will be programmed into SPI register. */
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ret = DIV_ROUND_UP(clk_get_rate(dspi->clk), max_speed_hz) - 1;
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if (ret < dspi->prescaler_limit || ret > 255)
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return -EINVAL;
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return ret;
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}
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/**
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* davinci_spi_setup_transfer - This functions will determine transfer method
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* @spi: spi device on which data transfer to be done
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* @t: spi transfer in which transfer info is filled
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*
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* This function determines data transfer method (8/16/32 bit transfer).
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* It will also set the SPI Clock Control register according to
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* SPI slave device freq.
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*/
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static int davinci_spi_setup_transfer(struct spi_device *spi,
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struct spi_transfer *t)
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{
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struct davinci_spi *dspi;
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struct davinci_spi_config *spicfg;
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u8 bits_per_word = 0;
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u32 hz = 0, spifmt = 0;
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int prescale;
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dspi = spi_master_get_devdata(spi->master);
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spicfg = spi->controller_data;
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if (!spicfg)
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spicfg = &davinci_spi_default_cfg;
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if (t) {
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bits_per_word = t->bits_per_word;
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hz = t->speed_hz;
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}
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/* if bits_per_word is not set then set it default */
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if (!bits_per_word)
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bits_per_word = spi->bits_per_word;
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/*
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* Assign function pointer to appropriate transfer method
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* 8bit, 16bit or 32bit transfer
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*/
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if (bits_per_word <= 8) {
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dspi->get_rx = davinci_spi_rx_buf_u8;
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dspi->get_tx = davinci_spi_tx_buf_u8;
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dspi->bytes_per_word[spi->chip_select] = 1;
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} else {
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dspi->get_rx = davinci_spi_rx_buf_u16;
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dspi->get_tx = davinci_spi_tx_buf_u16;
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dspi->bytes_per_word[spi->chip_select] = 2;
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}
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if (!hz)
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hz = spi->max_speed_hz;
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/* Set up SPIFMTn register, unique to this chipselect. */
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prescale = davinci_spi_get_prescale(dspi, hz);
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if (prescale < 0)
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return prescale;
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spifmt = (prescale << SPIFMT_PRESCALE_SHIFT) | (bits_per_word & 0x1f);
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if (spi->mode & SPI_LSB_FIRST)
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spifmt |= SPIFMT_SHIFTDIR_MASK;
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if (spi->mode & SPI_CPOL)
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spifmt |= SPIFMT_POLARITY_MASK;
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if (!(spi->mode & SPI_CPHA))
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spifmt |= SPIFMT_PHASE_MASK;
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/*
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* Assume wdelay is used only on SPI peripherals that has this field
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* in SPIFMTn register and when it's configured from board file or DT.
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*/
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if (spicfg->wdelay)
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spifmt |= ((spicfg->wdelay << SPIFMT_WDELAY_SHIFT)
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& SPIFMT_WDELAY_MASK);
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/*
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* Version 1 hardware supports two basic SPI modes:
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* - Standard SPI mode uses 4 pins, with chipselect
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* - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS)
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* (distinct from SPI_3WIRE, with just one data wire;
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* or similar variants without MOSI or without MISO)
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*
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* Version 2 hardware supports an optional handshaking signal,
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* so it can support two more modes:
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* - 5 pin SPI variant is standard SPI plus SPI_READY
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* - 4 pin with enable is (SPI_READY | SPI_NO_CS)
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*/
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if (dspi->version == SPI_VERSION_2) {
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u32 delay = 0;
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if (spicfg->odd_parity)
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spifmt |= SPIFMT_ODD_PARITY_MASK;
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if (spicfg->parity_enable)
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spifmt |= SPIFMT_PARITYENA_MASK;
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if (spicfg->timer_disable) {
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spifmt |= SPIFMT_DISTIMER_MASK;
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} else {
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delay |= (spicfg->c2tdelay << SPIDELAY_C2TDELAY_SHIFT)
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& SPIDELAY_C2TDELAY_MASK;
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delay |= (spicfg->t2cdelay << SPIDELAY_T2CDELAY_SHIFT)
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& SPIDELAY_T2CDELAY_MASK;
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}
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if (spi->mode & SPI_READY) {
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spifmt |= SPIFMT_WAITENA_MASK;
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delay |= (spicfg->t2edelay << SPIDELAY_T2EDELAY_SHIFT)
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& SPIDELAY_T2EDELAY_MASK;
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delay |= (spicfg->c2edelay << SPIDELAY_C2EDELAY_SHIFT)
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& SPIDELAY_C2EDELAY_MASK;
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}
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iowrite32(delay, dspi->base + SPIDELAY);
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}
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iowrite32(spifmt, dspi->base + SPIFMT0);
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return 0;
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}
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static int davinci_spi_of_setup(struct spi_device *spi)
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{
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struct davinci_spi_config *spicfg = spi->controller_data;
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struct device_node *np = spi->dev.of_node;
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struct davinci_spi *dspi = spi_master_get_devdata(spi->master);
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u32 prop;
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if (spicfg == NULL && np) {
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spicfg = kzalloc(sizeof(*spicfg), GFP_KERNEL);
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if (!spicfg)
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return -ENOMEM;
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*spicfg = davinci_spi_default_cfg;
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/* override with dt configured values */
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if (!of_property_read_u32(np, "ti,spi-wdelay", &prop))
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spicfg->wdelay = (u8)prop;
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spi->controller_data = spicfg;
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if (dspi->dma_rx && dspi->dma_tx)
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spicfg->io_type = SPI_IO_TYPE_DMA;
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}
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return 0;
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}
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/**
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* davinci_spi_setup - This functions will set default transfer method
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* @spi: spi device on which data transfer to be done
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*
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* This functions sets the default transfer method.
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*/
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static int davinci_spi_setup(struct spi_device *spi)
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{
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struct davinci_spi *dspi;
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struct device_node *np = spi->dev.of_node;
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bool internal_cs = true;
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dspi = spi_master_get_devdata(spi->master);
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if (!(spi->mode & SPI_NO_CS)) {
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if (np && spi->cs_gpiod)
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internal_cs = false;
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if (internal_cs)
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set_io_bits(dspi->base + SPIPC0, 1 << spi->chip_select);
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}
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if (spi->mode & SPI_READY)
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set_io_bits(dspi->base + SPIPC0, SPIPC0_SPIENA_MASK);
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if (spi->mode & SPI_LOOP)
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set_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);
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else
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clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);
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return davinci_spi_of_setup(spi);
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}
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static void davinci_spi_cleanup(struct spi_device *spi)
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{
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struct davinci_spi_config *spicfg = spi->controller_data;
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spi->controller_data = NULL;
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if (spi->dev.of_node)
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kfree(spicfg);
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}
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static bool davinci_spi_can_dma(struct spi_master *master,
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struct spi_device *spi,
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struct spi_transfer *xfer)
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{
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struct davinci_spi_config *spicfg = spi->controller_data;
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bool can_dma = false;
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if (spicfg)
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can_dma = (spicfg->io_type == SPI_IO_TYPE_DMA) &&
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(xfer->len >= DMA_MIN_BYTES) &&
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!is_vmalloc_addr(xfer->rx_buf) &&
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!is_vmalloc_addr(xfer->tx_buf);
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return can_dma;
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}
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static int davinci_spi_check_error(struct davinci_spi *dspi, int int_status)
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{
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struct device *sdev = dspi->bitbang.master->dev.parent;
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if (int_status & SPIFLG_TIMEOUT_MASK) {
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dev_err(sdev, "SPI Time-out Error\n");
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return -ETIMEDOUT;
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}
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if (int_status & SPIFLG_DESYNC_MASK) {
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dev_err(sdev, "SPI Desynchronization Error\n");
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return -EIO;
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}
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if (int_status & SPIFLG_BITERR_MASK) {
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dev_err(sdev, "SPI Bit error\n");
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return -EIO;
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}
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if (dspi->version == SPI_VERSION_2) {
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if (int_status & SPIFLG_DLEN_ERR_MASK) {
|
|
dev_err(sdev, "SPI Data Length Error\n");
|
|
return -EIO;
|
|
}
|
|
if (int_status & SPIFLG_PARERR_MASK) {
|
|
dev_err(sdev, "SPI Parity Error\n");
|
|
return -EIO;
|
|
}
|
|
if (int_status & SPIFLG_OVRRUN_MASK) {
|
|
dev_err(sdev, "SPI Data Overrun error\n");
|
|
return -EIO;
|
|
}
|
|
if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) {
|
|
dev_err(sdev, "SPI Buffer Init Active\n");
|
|
return -EBUSY;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* davinci_spi_process_events - check for and handle any SPI controller events
|
|
* @dspi: the controller data
|
|
*
|
|
* This function will check the SPIFLG register and handle any events that are
|
|
* detected there
|
|
*/
|
|
static int davinci_spi_process_events(struct davinci_spi *dspi)
|
|
{
|
|
u32 buf, status, errors = 0, spidat1;
|
|
|
|
buf = ioread32(dspi->base + SPIBUF);
|
|
|
|
if (dspi->rcount > 0 && !(buf & SPIBUF_RXEMPTY_MASK)) {
|
|
dspi->get_rx(buf & 0xFFFF, dspi);
|
|
dspi->rcount--;
|
|
}
|
|
|
|
status = ioread32(dspi->base + SPIFLG);
|
|
|
|
if (unlikely(status & SPIFLG_ERROR_MASK)) {
|
|
errors = status & SPIFLG_ERROR_MASK;
|
|
goto out;
|
|
}
|
|
|
|
if (dspi->wcount > 0 && !(buf & SPIBUF_TXFULL_MASK)) {
|
|
spidat1 = ioread32(dspi->base + SPIDAT1);
|
|
dspi->wcount--;
|
|
spidat1 &= ~0xFFFF;
|
|
spidat1 |= 0xFFFF & dspi->get_tx(dspi);
|
|
iowrite32(spidat1, dspi->base + SPIDAT1);
|
|
}
|
|
|
|
out:
|
|
return errors;
|
|
}
|
|
|
|
static void davinci_spi_dma_rx_callback(void *data)
|
|
{
|
|
struct davinci_spi *dspi = (struct davinci_spi *)data;
|
|
|
|
dspi->rcount = 0;
|
|
|
|
if (!dspi->wcount && !dspi->rcount)
|
|
complete(&dspi->done);
|
|
}
|
|
|
|
static void davinci_spi_dma_tx_callback(void *data)
|
|
{
|
|
struct davinci_spi *dspi = (struct davinci_spi *)data;
|
|
|
|
dspi->wcount = 0;
|
|
|
|
if (!dspi->wcount && !dspi->rcount)
|
|
complete(&dspi->done);
|
|
}
|
|
|
|
/**
|
|
* davinci_spi_bufs - functions which will handle transfer data
|
|
* @spi: spi device on which data transfer to be done
|
|
* @t: spi transfer in which transfer info is filled
|
|
*
|
|
* This function will put data to be transferred into data register
|
|
* of SPI controller and then wait until the completion will be marked
|
|
* by the IRQ Handler.
|
|
*/
|
|
static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
|
|
{
|
|
struct davinci_spi *dspi;
|
|
int data_type, ret = -ENOMEM;
|
|
u32 tx_data, spidat1;
|
|
u32 errors = 0;
|
|
struct davinci_spi_config *spicfg;
|
|
struct davinci_spi_platform_data *pdata;
|
|
|
|
dspi = spi_master_get_devdata(spi->master);
|
|
pdata = &dspi->pdata;
|
|
spicfg = (struct davinci_spi_config *)spi->controller_data;
|
|
if (!spicfg)
|
|
spicfg = &davinci_spi_default_cfg;
|
|
|
|
/* convert len to words based on bits_per_word */
|
|
data_type = dspi->bytes_per_word[spi->chip_select];
|
|
|
|
dspi->tx = t->tx_buf;
|
|
dspi->rx = t->rx_buf;
|
|
dspi->wcount = t->len / data_type;
|
|
dspi->rcount = dspi->wcount;
|
|
|
|
spidat1 = ioread32(dspi->base + SPIDAT1);
|
|
|
|
clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
|
|
set_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
|
|
|
|
reinit_completion(&dspi->done);
|
|
|
|
if (!davinci_spi_can_dma(spi->master, spi, t)) {
|
|
if (spicfg->io_type != SPI_IO_TYPE_POLL)
|
|
set_io_bits(dspi->base + SPIINT, SPIINT_MASKINT);
|
|
/* start the transfer */
|
|
dspi->wcount--;
|
|
tx_data = dspi->get_tx(dspi);
|
|
spidat1 &= 0xFFFF0000;
|
|
spidat1 |= tx_data & 0xFFFF;
|
|
iowrite32(spidat1, dspi->base + SPIDAT1);
|
|
} else {
|
|
struct dma_slave_config dma_rx_conf = {
|
|
.direction = DMA_DEV_TO_MEM,
|
|
.src_addr = (unsigned long)dspi->pbase + SPIBUF,
|
|
.src_addr_width = data_type,
|
|
.src_maxburst = 1,
|
|
};
|
|
struct dma_slave_config dma_tx_conf = {
|
|
.direction = DMA_MEM_TO_DEV,
|
|
.dst_addr = (unsigned long)dspi->pbase + SPIDAT1,
|
|
.dst_addr_width = data_type,
|
|
.dst_maxburst = 1,
|
|
};
|
|
struct dma_async_tx_descriptor *rxdesc;
|
|
struct dma_async_tx_descriptor *txdesc;
|
|
|
|
dmaengine_slave_config(dspi->dma_rx, &dma_rx_conf);
|
|
dmaengine_slave_config(dspi->dma_tx, &dma_tx_conf);
|
|
|
|
rxdesc = dmaengine_prep_slave_sg(dspi->dma_rx,
|
|
t->rx_sg.sgl, t->rx_sg.nents, DMA_DEV_TO_MEM,
|
|
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
|
|
if (!rxdesc)
|
|
goto err_desc;
|
|
|
|
if (!t->tx_buf) {
|
|
/* To avoid errors when doing rx-only transfers with
|
|
* many SG entries (> 20), use the rx buffer as the
|
|
* dummy tx buffer so that dma reloads are done at the
|
|
* same time for rx and tx.
|
|
*/
|
|
t->tx_sg.sgl = t->rx_sg.sgl;
|
|
t->tx_sg.nents = t->rx_sg.nents;
|
|
}
|
|
|
|
txdesc = dmaengine_prep_slave_sg(dspi->dma_tx,
|
|
t->tx_sg.sgl, t->tx_sg.nents, DMA_MEM_TO_DEV,
|
|
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
|
|
if (!txdesc)
|
|
goto err_desc;
|
|
|
|
rxdesc->callback = davinci_spi_dma_rx_callback;
|
|
rxdesc->callback_param = (void *)dspi;
|
|
txdesc->callback = davinci_spi_dma_tx_callback;
|
|
txdesc->callback_param = (void *)dspi;
|
|
|
|
if (pdata->cshold_bug)
|
|
iowrite16(spidat1 >> 16, dspi->base + SPIDAT1 + 2);
|
|
|
|
dmaengine_submit(rxdesc);
|
|
dmaengine_submit(txdesc);
|
|
|
|
dma_async_issue_pending(dspi->dma_rx);
|
|
dma_async_issue_pending(dspi->dma_tx);
|
|
|
|
set_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
|
|
}
|
|
|
|
/* Wait for the transfer to complete */
|
|
if (spicfg->io_type != SPI_IO_TYPE_POLL) {
|
|
if (wait_for_completion_timeout(&dspi->done, HZ) == 0)
|
|
errors = SPIFLG_TIMEOUT_MASK;
|
|
} else {
|
|
while (dspi->rcount > 0 || dspi->wcount > 0) {
|
|
errors = davinci_spi_process_events(dspi);
|
|
if (errors)
|
|
break;
|
|
cpu_relax();
|
|
}
|
|
}
|
|
|
|
clear_io_bits(dspi->base + SPIINT, SPIINT_MASKALL);
|
|
if (davinci_spi_can_dma(spi->master, spi, t))
|
|
clear_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
|
|
|
|
clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
|
|
set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
|
|
|
|
/*
|
|
* Check for bit error, desync error,parity error,timeout error and
|
|
* receive overflow errors
|
|
*/
|
|
if (errors) {
|
|
ret = davinci_spi_check_error(dspi, errors);
|
|
WARN(!ret, "%s: error reported but no error found!\n",
|
|
dev_name(&spi->dev));
|
|
return ret;
|
|
}
|
|
|
|
if (dspi->rcount != 0 || dspi->wcount != 0) {
|
|
dev_err(&spi->dev, "SPI data transfer error\n");
|
|
return -EIO;
|
|
}
|
|
|
|
return t->len;
|
|
|
|
err_desc:
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* dummy_thread_fn - dummy thread function
|
|
* @irq: IRQ number for this SPI Master
|
|
* @data: structure for SPI Master controller davinci_spi
|
|
*
|
|
* This is to satisfy the request_threaded_irq() API so that the irq
|
|
* handler is called in interrupt context.
|
|
*/
|
|
static irqreturn_t dummy_thread_fn(s32 irq, void *data)
|
|
{
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
/**
|
|
* davinci_spi_irq - Interrupt handler for SPI Master Controller
|
|
* @irq: IRQ number for this SPI Master
|
|
* @data: structure for SPI Master controller davinci_spi
|
|
*
|
|
* ISR will determine that interrupt arrives either for READ or WRITE command.
|
|
* According to command it will do the appropriate action. It will check
|
|
* transfer length and if it is not zero then dispatch transfer command again.
|
|
* If transfer length is zero then it will indicate the COMPLETION so that
|
|
* davinci_spi_bufs function can go ahead.
|
|
*/
|
|
static irqreturn_t davinci_spi_irq(s32 irq, void *data)
|
|
{
|
|
struct davinci_spi *dspi = data;
|
|
int status;
|
|
|
|
status = davinci_spi_process_events(dspi);
|
|
if (unlikely(status != 0))
|
|
clear_io_bits(dspi->base + SPIINT, SPIINT_MASKINT);
|
|
|
|
if ((!dspi->rcount && !dspi->wcount) || status)
|
|
complete(&dspi->done);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static int davinci_spi_request_dma(struct davinci_spi *dspi)
|
|
{
|
|
struct device *sdev = dspi->bitbang.master->dev.parent;
|
|
|
|
dspi->dma_rx = dma_request_chan(sdev, "rx");
|
|
if (IS_ERR(dspi->dma_rx))
|
|
return PTR_ERR(dspi->dma_rx);
|
|
|
|
dspi->dma_tx = dma_request_chan(sdev, "tx");
|
|
if (IS_ERR(dspi->dma_tx)) {
|
|
dma_release_channel(dspi->dma_rx);
|
|
return PTR_ERR(dspi->dma_tx);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
#if defined(CONFIG_OF)
|
|
|
|
/* OF SPI data structure */
|
|
struct davinci_spi_of_data {
|
|
u8 version;
|
|
u8 prescaler_limit;
|
|
};
|
|
|
|
static const struct davinci_spi_of_data dm6441_spi_data = {
|
|
.version = SPI_VERSION_1,
|
|
.prescaler_limit = 2,
|
|
};
|
|
|
|
static const struct davinci_spi_of_data da830_spi_data = {
|
|
.version = SPI_VERSION_2,
|
|
.prescaler_limit = 2,
|
|
};
|
|
|
|
static const struct davinci_spi_of_data keystone_spi_data = {
|
|
.version = SPI_VERSION_1,
|
|
.prescaler_limit = 0,
|
|
};
|
|
|
|
static const struct of_device_id davinci_spi_of_match[] = {
|
|
{
|
|
.compatible = "ti,dm6441-spi",
|
|
.data = &dm6441_spi_data,
|
|
},
|
|
{
|
|
.compatible = "ti,da830-spi",
|
|
.data = &da830_spi_data,
|
|
},
|
|
{
|
|
.compatible = "ti,keystone-spi",
|
|
.data = &keystone_spi_data,
|
|
},
|
|
{ },
|
|
};
|
|
MODULE_DEVICE_TABLE(of, davinci_spi_of_match);
|
|
|
|
/**
|
|
* spi_davinci_get_pdata - Get platform data from DTS binding
|
|
* @pdev: ptr to platform data
|
|
* @dspi: ptr to driver data
|
|
*
|
|
* Parses and populates pdata in dspi from device tree bindings.
|
|
*
|
|
* NOTE: Not all platform data params are supported currently.
|
|
*/
|
|
static int spi_davinci_get_pdata(struct platform_device *pdev,
|
|
struct davinci_spi *dspi)
|
|
{
|
|
struct device_node *node = pdev->dev.of_node;
|
|
const struct davinci_spi_of_data *spi_data;
|
|
struct davinci_spi_platform_data *pdata;
|
|
unsigned int num_cs, intr_line = 0;
|
|
|
|
pdata = &dspi->pdata;
|
|
|
|
spi_data = device_get_match_data(&pdev->dev);
|
|
|
|
pdata->version = spi_data->version;
|
|
pdata->prescaler_limit = spi_data->prescaler_limit;
|
|
/*
|
|
* default num_cs is 1 and all chipsel are internal to the chip
|
|
* indicated by chip_sel being NULL or cs_gpios being NULL or
|
|
* set to -ENOENT. num-cs includes internal as well as gpios.
|
|
* indicated by chip_sel being NULL. GPIO based CS is not
|
|
* supported yet in DT bindings.
|
|
*/
|
|
num_cs = 1;
|
|
of_property_read_u32(node, "num-cs", &num_cs);
|
|
pdata->num_chipselect = num_cs;
|
|
of_property_read_u32(node, "ti,davinci-spi-intr-line", &intr_line);
|
|
pdata->intr_line = intr_line;
|
|
return 0;
|
|
}
|
|
#else
|
|
static int spi_davinci_get_pdata(struct platform_device *pdev,
|
|
struct davinci_spi *dspi)
|
|
{
|
|
return -ENODEV;
|
|
}
|
|
#endif
|
|
|
|
/**
|
|
* davinci_spi_probe - probe function for SPI Master Controller
|
|
* @pdev: platform_device structure which contains plateform specific data
|
|
*
|
|
* According to Linux Device Model this function will be invoked by Linux
|
|
* with platform_device struct which contains the device specific info.
|
|
* This function will map the SPI controller's memory, register IRQ,
|
|
* Reset SPI controller and setting its registers to default value.
|
|
* It will invoke spi_bitbang_start to create work queue so that client driver
|
|
* can register transfer method to work queue.
|
|
*/
|
|
static int davinci_spi_probe(struct platform_device *pdev)
|
|
{
|
|
struct spi_master *master;
|
|
struct davinci_spi *dspi;
|
|
struct davinci_spi_platform_data *pdata;
|
|
struct resource *r;
|
|
int ret = 0;
|
|
u32 spipc0;
|
|
|
|
master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi));
|
|
if (master == NULL) {
|
|
ret = -ENOMEM;
|
|
goto err;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, master);
|
|
|
|
dspi = spi_master_get_devdata(master);
|
|
|
|
if (dev_get_platdata(&pdev->dev)) {
|
|
pdata = dev_get_platdata(&pdev->dev);
|
|
dspi->pdata = *pdata;
|
|
} else {
|
|
/* update dspi pdata with that from the DT */
|
|
ret = spi_davinci_get_pdata(pdev, dspi);
|
|
if (ret < 0)
|
|
goto free_master;
|
|
}
|
|
|
|
/* pdata in dspi is now updated and point pdata to that */
|
|
pdata = &dspi->pdata;
|
|
|
|
dspi->bytes_per_word = devm_kcalloc(&pdev->dev,
|
|
pdata->num_chipselect,
|
|
sizeof(*dspi->bytes_per_word),
|
|
GFP_KERNEL);
|
|
if (dspi->bytes_per_word == NULL) {
|
|
ret = -ENOMEM;
|
|
goto free_master;
|
|
}
|
|
|
|
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (r == NULL) {
|
|
ret = -ENOENT;
|
|
goto free_master;
|
|
}
|
|
|
|
dspi->pbase = r->start;
|
|
|
|
dspi->base = devm_ioremap_resource(&pdev->dev, r);
|
|
if (IS_ERR(dspi->base)) {
|
|
ret = PTR_ERR(dspi->base);
|
|
goto free_master;
|
|
}
|
|
|
|
init_completion(&dspi->done);
|
|
|
|
ret = platform_get_irq(pdev, 0);
|
|
if (ret == 0)
|
|
ret = -EINVAL;
|
|
if (ret < 0)
|
|
goto free_master;
|
|
dspi->irq = ret;
|
|
|
|
ret = devm_request_threaded_irq(&pdev->dev, dspi->irq, davinci_spi_irq,
|
|
dummy_thread_fn, 0, dev_name(&pdev->dev), dspi);
|
|
if (ret)
|
|
goto free_master;
|
|
|
|
dspi->bitbang.master = master;
|
|
|
|
dspi->clk = devm_clk_get(&pdev->dev, NULL);
|
|
if (IS_ERR(dspi->clk)) {
|
|
ret = -ENODEV;
|
|
goto free_master;
|
|
}
|
|
ret = clk_prepare_enable(dspi->clk);
|
|
if (ret)
|
|
goto free_master;
|
|
|
|
master->use_gpio_descriptors = true;
|
|
master->dev.of_node = pdev->dev.of_node;
|
|
master->bus_num = pdev->id;
|
|
master->num_chipselect = pdata->num_chipselect;
|
|
master->bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 16);
|
|
master->flags = SPI_MASTER_MUST_RX | SPI_MASTER_GPIO_SS;
|
|
master->setup = davinci_spi_setup;
|
|
master->cleanup = davinci_spi_cleanup;
|
|
master->can_dma = davinci_spi_can_dma;
|
|
|
|
dspi->bitbang.chipselect = davinci_spi_chipselect;
|
|
dspi->bitbang.setup_transfer = davinci_spi_setup_transfer;
|
|
dspi->prescaler_limit = pdata->prescaler_limit;
|
|
dspi->version = pdata->version;
|
|
|
|
dspi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP | SPI_CS_WORD;
|
|
if (dspi->version == SPI_VERSION_2)
|
|
dspi->bitbang.flags |= SPI_READY;
|
|
|
|
dspi->bitbang.txrx_bufs = davinci_spi_bufs;
|
|
|
|
ret = davinci_spi_request_dma(dspi);
|
|
if (ret == -EPROBE_DEFER) {
|
|
goto free_clk;
|
|
} else if (ret) {
|
|
dev_info(&pdev->dev, "DMA is not supported (%d)\n", ret);
|
|
dspi->dma_rx = NULL;
|
|
dspi->dma_tx = NULL;
|
|
}
|
|
|
|
dspi->get_rx = davinci_spi_rx_buf_u8;
|
|
dspi->get_tx = davinci_spi_tx_buf_u8;
|
|
|
|
/* Reset In/OUT SPI module */
|
|
iowrite32(0, dspi->base + SPIGCR0);
|
|
udelay(100);
|
|
iowrite32(1, dspi->base + SPIGCR0);
|
|
|
|
/* Set up SPIPC0. CS and ENA init is done in davinci_spi_setup */
|
|
spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK;
|
|
iowrite32(spipc0, dspi->base + SPIPC0);
|
|
|
|
if (pdata->intr_line)
|
|
iowrite32(SPI_INTLVL_1, dspi->base + SPILVL);
|
|
else
|
|
iowrite32(SPI_INTLVL_0, dspi->base + SPILVL);
|
|
|
|
iowrite32(CS_DEFAULT, dspi->base + SPIDEF);
|
|
|
|
/* master mode default */
|
|
set_io_bits(dspi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK);
|
|
set_io_bits(dspi->base + SPIGCR1, SPIGCR1_MASTER_MASK);
|
|
set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
|
|
|
|
ret = spi_bitbang_start(&dspi->bitbang);
|
|
if (ret)
|
|
goto free_dma;
|
|
|
|
dev_info(&pdev->dev, "Controller at 0x%p\n", dspi->base);
|
|
|
|
return ret;
|
|
|
|
free_dma:
|
|
if (dspi->dma_rx) {
|
|
dma_release_channel(dspi->dma_rx);
|
|
dma_release_channel(dspi->dma_tx);
|
|
}
|
|
free_clk:
|
|
clk_disable_unprepare(dspi->clk);
|
|
free_master:
|
|
spi_master_put(master);
|
|
err:
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* davinci_spi_remove - remove function for SPI Master Controller
|
|
* @pdev: platform_device structure which contains plateform specific data
|
|
*
|
|
* This function will do the reverse action of davinci_spi_probe function
|
|
* It will free the IRQ and SPI controller's memory region.
|
|
* It will also call spi_bitbang_stop to destroy the work queue which was
|
|
* created by spi_bitbang_start.
|
|
*/
|
|
static int davinci_spi_remove(struct platform_device *pdev)
|
|
{
|
|
struct davinci_spi *dspi;
|
|
struct spi_master *master;
|
|
|
|
master = platform_get_drvdata(pdev);
|
|
dspi = spi_master_get_devdata(master);
|
|
|
|
spi_bitbang_stop(&dspi->bitbang);
|
|
|
|
clk_disable_unprepare(dspi->clk);
|
|
|
|
if (dspi->dma_rx) {
|
|
dma_release_channel(dspi->dma_rx);
|
|
dma_release_channel(dspi->dma_tx);
|
|
}
|
|
|
|
spi_master_put(master);
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver davinci_spi_driver = {
|
|
.driver = {
|
|
.name = "spi_davinci",
|
|
.of_match_table = of_match_ptr(davinci_spi_of_match),
|
|
},
|
|
.probe = davinci_spi_probe,
|
|
.remove = davinci_spi_remove,
|
|
};
|
|
module_platform_driver(davinci_spi_driver);
|
|
|
|
MODULE_DESCRIPTION("TI DaVinci SPI Master Controller Driver");
|
|
MODULE_LICENSE("GPL");
|