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![周琰杰 (Zhou Yanjie)](/assets/img/avatar_default.png)
1.Since it would be dangerous to specify a newer SoC's compatible string as the fallback of an older SoC's compatible string, we add support for the "ingenic,jz4775-spi" compatible string in the driver. This will permit to support the JZ4775 by having: compatible = "ingenic,jz4775-spi"; Instead of doing: compatible = "ingenic,jz4775-spi", "ingenic,jz4780-spi"; 2.Add support for probing the spi-ingenic driver on the X1000 SoC from Ingenic. From the X1000 SoC onwards, the maximum frequency allowed by the SSI module of Ingenic SoCs has been changed from 54MHz to 50MHz. So "max_speed_hz" is introduced in "jz_soc_info" to set different maximum frequency values. 3.Add support for probing the spi-ingenic driver on the X2000 SoC from Ingenic. The X2000 SoC has only one native chip select line, so "max_native_cs" is introduced in "jz_soc_info" to set different maximum number of native chip select lines. 4.Because of the introduction of support for the X-series SoCs, the current driver is not only applicable to the JZ-series SoCs, so the description texts has been modified to avoid misunderstanding. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/1650724725-93758-4-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Mark Brown <broonie@kernel.org>
519 lines
14 KiB
C
519 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* SPI bus driver for the Ingenic SoCs
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* Copyright (c) 2017-2021 Artur Rojek <contact@artur-rojek.eu>
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* Copyright (c) 2017-2021 Paul Cercueil <paul@crapouillou.net>
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* Copyright (c) 2022 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/dmaengine.h>
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#include <linux/dma-mapping.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/spi/spi.h>
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#define REG_SSIDR 0x0
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#define REG_SSICR0 0x4
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#define REG_SSICR1 0x8
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#define REG_SSISR 0xc
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#define REG_SSIGR 0x18
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#define REG_SSICR0_TENDIAN_LSB BIT(19)
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#define REG_SSICR0_RENDIAN_LSB BIT(17)
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#define REG_SSICR0_SSIE BIT(15)
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#define REG_SSICR0_LOOP BIT(10)
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#define REG_SSICR0_EACLRUN BIT(7)
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#define REG_SSICR0_FSEL BIT(6)
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#define REG_SSICR0_TFLUSH BIT(2)
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#define REG_SSICR0_RFLUSH BIT(1)
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#define REG_SSICR1_FRMHL_MASK (BIT(31) | BIT(30))
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#define REG_SSICR1_FRMHL BIT(30)
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#define REG_SSICR1_LFST BIT(25)
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#define REG_SSICR1_UNFIN BIT(23)
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#define REG_SSICR1_PHA BIT(1)
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#define REG_SSICR1_POL BIT(0)
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#define REG_SSISR_END BIT(7)
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#define REG_SSISR_BUSY BIT(6)
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#define REG_SSISR_TFF BIT(5)
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#define REG_SSISR_RFE BIT(4)
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#define REG_SSISR_RFHF BIT(2)
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#define REG_SSISR_UNDR BIT(1)
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#define REG_SSISR_OVER BIT(0)
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#define SPI_INGENIC_FIFO_SIZE 128u
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struct jz_soc_info {
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u32 bits_per_word_mask;
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struct reg_field flen_field;
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bool has_trendian;
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unsigned int max_speed_hz;
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unsigned int max_native_cs;
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};
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struct ingenic_spi {
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const struct jz_soc_info *soc_info;
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struct clk *clk;
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struct resource *mem_res;
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struct regmap *map;
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struct regmap_field *flen_field;
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};
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static int spi_ingenic_wait(struct ingenic_spi *priv,
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unsigned long mask,
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bool condition)
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{
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unsigned int val;
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return regmap_read_poll_timeout(priv->map, REG_SSISR, val,
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!!(val & mask) == condition,
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100, 10000);
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}
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static void spi_ingenic_set_cs(struct spi_device *spi, bool disable)
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{
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struct ingenic_spi *priv = spi_controller_get_devdata(spi->controller);
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if (disable) {
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regmap_clear_bits(priv->map, REG_SSICR1, REG_SSICR1_UNFIN);
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regmap_clear_bits(priv->map, REG_SSISR,
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REG_SSISR_UNDR | REG_SSISR_OVER);
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spi_ingenic_wait(priv, REG_SSISR_END, true);
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} else {
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regmap_set_bits(priv->map, REG_SSICR1, REG_SSICR1_UNFIN);
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}
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regmap_set_bits(priv->map, REG_SSICR0,
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REG_SSICR0_RFLUSH | REG_SSICR0_TFLUSH);
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}
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static void spi_ingenic_prepare_transfer(struct ingenic_spi *priv,
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struct spi_device *spi,
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struct spi_transfer *xfer)
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{
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unsigned long clk_hz = clk_get_rate(priv->clk);
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u32 cdiv, speed_hz = xfer->speed_hz ?: spi->max_speed_hz,
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bits_per_word = xfer->bits_per_word ?: spi->bits_per_word;
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cdiv = clk_hz / (speed_hz * 2);
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cdiv = clamp(cdiv, 1u, 0x100u) - 1;
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regmap_write(priv->map, REG_SSIGR, cdiv);
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regmap_field_write(priv->flen_field, bits_per_word - 2);
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}
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static void spi_ingenic_finalize_transfer(void *controller)
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{
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spi_finalize_current_transfer(controller);
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}
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static struct dma_async_tx_descriptor *
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spi_ingenic_prepare_dma(struct spi_controller *ctlr, struct dma_chan *chan,
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struct sg_table *sg, enum dma_transfer_direction dir,
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unsigned int bits)
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{
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struct ingenic_spi *priv = spi_controller_get_devdata(ctlr);
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struct dma_slave_config cfg = {
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.direction = dir,
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.src_addr = priv->mem_res->start + REG_SSIDR,
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.dst_addr = priv->mem_res->start + REG_SSIDR,
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};
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struct dma_async_tx_descriptor *desc;
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dma_cookie_t cookie;
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int ret;
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if (bits > 16) {
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cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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cfg.src_maxburst = cfg.dst_maxburst = 4;
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} else if (bits > 8) {
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cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
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cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
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cfg.src_maxburst = cfg.dst_maxburst = 2;
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} else {
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cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
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cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
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cfg.src_maxburst = cfg.dst_maxburst = 1;
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}
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ret = dmaengine_slave_config(chan, &cfg);
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if (ret)
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return ERR_PTR(ret);
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desc = dmaengine_prep_slave_sg(chan, sg->sgl, sg->nents, dir,
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DMA_PREP_INTERRUPT);
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if (!desc)
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return ERR_PTR(-ENOMEM);
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if (dir == DMA_DEV_TO_MEM) {
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desc->callback = spi_ingenic_finalize_transfer;
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desc->callback_param = ctlr;
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}
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cookie = dmaengine_submit(desc);
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ret = dma_submit_error(cookie);
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if (ret) {
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dmaengine_desc_free(desc);
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return ERR_PTR(ret);
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}
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return desc;
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}
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static int spi_ingenic_dma_tx(struct spi_controller *ctlr,
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struct spi_transfer *xfer, unsigned int bits)
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{
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struct dma_async_tx_descriptor *rx_desc, *tx_desc;
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rx_desc = spi_ingenic_prepare_dma(ctlr, ctlr->dma_rx,
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&xfer->rx_sg, DMA_DEV_TO_MEM, bits);
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if (IS_ERR(rx_desc))
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return PTR_ERR(rx_desc);
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tx_desc = spi_ingenic_prepare_dma(ctlr, ctlr->dma_tx,
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&xfer->tx_sg, DMA_MEM_TO_DEV, bits);
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if (IS_ERR(tx_desc)) {
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dmaengine_terminate_async(ctlr->dma_rx);
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dmaengine_desc_free(rx_desc);
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return PTR_ERR(tx_desc);
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}
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dma_async_issue_pending(ctlr->dma_rx);
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dma_async_issue_pending(ctlr->dma_tx);
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return 1;
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}
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#define SPI_INGENIC_TX(x) \
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static int spi_ingenic_tx##x(struct ingenic_spi *priv, \
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struct spi_transfer *xfer) \
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{ \
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unsigned int count = xfer->len / (x / 8); \
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unsigned int prefill = min(count, SPI_INGENIC_FIFO_SIZE); \
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const u##x *tx_buf = xfer->tx_buf; \
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u##x *rx_buf = xfer->rx_buf; \
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unsigned int i, val; \
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int err; \
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\
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/* Fill up the TX fifo */ \
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for (i = 0; i < prefill; i++) { \
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val = tx_buf ? tx_buf[i] : 0; \
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\
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regmap_write(priv->map, REG_SSIDR, val); \
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} \
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\
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for (i = 0; i < count; i++) { \
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err = spi_ingenic_wait(priv, REG_SSISR_RFE, false); \
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if (err) \
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return err; \
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\
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regmap_read(priv->map, REG_SSIDR, &val); \
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if (rx_buf) \
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rx_buf[i] = val; \
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\
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if (i < count - prefill) { \
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val = tx_buf ? tx_buf[i + prefill] : 0; \
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\
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regmap_write(priv->map, REG_SSIDR, val); \
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} \
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} \
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\
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return 0; \
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}
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SPI_INGENIC_TX(8)
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SPI_INGENIC_TX(16)
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SPI_INGENIC_TX(32)
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#undef SPI_INGENIC_TX
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static int spi_ingenic_transfer_one(struct spi_controller *ctlr,
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struct spi_device *spi,
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struct spi_transfer *xfer)
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{
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struct ingenic_spi *priv = spi_controller_get_devdata(ctlr);
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unsigned int bits = xfer->bits_per_word ?: spi->bits_per_word;
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bool can_dma = ctlr->can_dma && ctlr->can_dma(ctlr, spi, xfer);
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spi_ingenic_prepare_transfer(priv, spi, xfer);
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if (ctlr->cur_msg_mapped && can_dma)
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return spi_ingenic_dma_tx(ctlr, xfer, bits);
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if (bits > 16)
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return spi_ingenic_tx32(priv, xfer);
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if (bits > 8)
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return spi_ingenic_tx16(priv, xfer);
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return spi_ingenic_tx8(priv, xfer);
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}
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static int spi_ingenic_prepare_message(struct spi_controller *ctlr,
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struct spi_message *message)
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{
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struct ingenic_spi *priv = spi_controller_get_devdata(ctlr);
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struct spi_device *spi = message->spi;
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unsigned int cs = REG_SSICR1_FRMHL << spi->chip_select;
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unsigned int ssicr0_mask = REG_SSICR0_LOOP | REG_SSICR0_FSEL;
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unsigned int ssicr1_mask = REG_SSICR1_PHA | REG_SSICR1_POL | cs;
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unsigned int ssicr0 = 0, ssicr1 = 0;
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if (priv->soc_info->has_trendian) {
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ssicr0_mask |= REG_SSICR0_RENDIAN_LSB | REG_SSICR0_TENDIAN_LSB;
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if (spi->mode & SPI_LSB_FIRST)
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ssicr0 |= REG_SSICR0_RENDIAN_LSB | REG_SSICR0_TENDIAN_LSB;
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} else {
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ssicr1_mask |= REG_SSICR1_LFST;
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if (spi->mode & SPI_LSB_FIRST)
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ssicr1 |= REG_SSICR1_LFST;
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}
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if (spi->mode & SPI_LOOP)
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ssicr0 |= REG_SSICR0_LOOP;
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if (spi->chip_select)
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ssicr0 |= REG_SSICR0_FSEL;
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if (spi->mode & SPI_CPHA)
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ssicr1 |= REG_SSICR1_PHA;
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if (spi->mode & SPI_CPOL)
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ssicr1 |= REG_SSICR1_POL;
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if (spi->mode & SPI_CS_HIGH)
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ssicr1 |= cs;
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regmap_update_bits(priv->map, REG_SSICR0, ssicr0_mask, ssicr0);
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regmap_update_bits(priv->map, REG_SSICR1, ssicr1_mask, ssicr1);
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return 0;
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}
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static int spi_ingenic_prepare_hardware(struct spi_controller *ctlr)
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{
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struct ingenic_spi *priv = spi_controller_get_devdata(ctlr);
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int ret;
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ret = clk_prepare_enable(priv->clk);
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if (ret)
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return ret;
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regmap_write(priv->map, REG_SSICR0, REG_SSICR0_EACLRUN);
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regmap_write(priv->map, REG_SSICR1, 0);
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regmap_write(priv->map, REG_SSISR, 0);
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regmap_set_bits(priv->map, REG_SSICR0, REG_SSICR0_SSIE);
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return 0;
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}
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static int spi_ingenic_unprepare_hardware(struct spi_controller *ctlr)
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{
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struct ingenic_spi *priv = spi_controller_get_devdata(ctlr);
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regmap_clear_bits(priv->map, REG_SSICR0, REG_SSICR0_SSIE);
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clk_disable_unprepare(priv->clk);
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return 0;
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}
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static bool spi_ingenic_can_dma(struct spi_controller *ctlr,
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struct spi_device *spi,
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struct spi_transfer *xfer)
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{
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struct dma_slave_caps caps;
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int ret;
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ret = dma_get_slave_caps(ctlr->dma_tx, &caps);
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if (ret) {
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dev_err(&spi->dev, "Unable to get slave caps: %d\n", ret);
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return false;
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}
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return !caps.max_sg_burst ||
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xfer->len <= caps.max_sg_burst * SPI_INGENIC_FIFO_SIZE;
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}
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static int spi_ingenic_request_dma(struct spi_controller *ctlr,
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struct device *dev)
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{
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ctlr->dma_tx = dma_request_slave_channel(dev, "tx");
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if (!ctlr->dma_tx)
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return -ENODEV;
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ctlr->dma_rx = dma_request_slave_channel(dev, "rx");
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if (!ctlr->dma_rx)
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return -ENODEV;
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ctlr->can_dma = spi_ingenic_can_dma;
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return 0;
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}
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static void spi_ingenic_release_dma(void *data)
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{
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struct spi_controller *ctlr = data;
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if (ctlr->dma_tx)
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dma_release_channel(ctlr->dma_tx);
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if (ctlr->dma_rx)
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dma_release_channel(ctlr->dma_rx);
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}
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static const struct regmap_config spi_ingenic_regmap_config = {
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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.max_register = REG_SSIGR,
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};
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static int spi_ingenic_probe(struct platform_device *pdev)
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{
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const struct jz_soc_info *pdata;
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struct device *dev = &pdev->dev;
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struct spi_controller *ctlr;
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struct ingenic_spi *priv;
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void __iomem *base;
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int num_cs, ret;
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pdata = of_device_get_match_data(dev);
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if (!pdata) {
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dev_err(dev, "Missing platform data.\n");
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return -EINVAL;
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}
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ctlr = devm_spi_alloc_master(dev, sizeof(*priv));
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if (!ctlr) {
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dev_err(dev, "Unable to allocate SPI controller.\n");
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return -ENOMEM;
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}
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priv = spi_controller_get_devdata(ctlr);
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priv->soc_info = pdata;
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priv->clk = devm_clk_get(dev, NULL);
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if (IS_ERR(priv->clk)) {
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return dev_err_probe(dev, PTR_ERR(priv->clk),
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"Unable to get clock.\n");
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}
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base = devm_platform_get_and_ioremap_resource(pdev, 0, &priv->mem_res);
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if (IS_ERR(base))
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return PTR_ERR(base);
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priv->map = devm_regmap_init_mmio(dev, base, &spi_ingenic_regmap_config);
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if (IS_ERR(priv->map))
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return PTR_ERR(priv->map);
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priv->flen_field = devm_regmap_field_alloc(dev, priv->map,
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pdata->flen_field);
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if (IS_ERR(priv->flen_field))
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return PTR_ERR(priv->flen_field);
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if (device_property_read_u32(dev, "num-cs", &num_cs))
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num_cs = pdata->max_native_cs;
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platform_set_drvdata(pdev, ctlr);
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ctlr->prepare_transfer_hardware = spi_ingenic_prepare_hardware;
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ctlr->unprepare_transfer_hardware = spi_ingenic_unprepare_hardware;
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ctlr->prepare_message = spi_ingenic_prepare_message;
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ctlr->set_cs = spi_ingenic_set_cs;
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ctlr->transfer_one = spi_ingenic_transfer_one;
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ctlr->mode_bits = SPI_MODE_3 | SPI_LSB_FIRST | SPI_LOOP | SPI_CS_HIGH;
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ctlr->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX;
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ctlr->max_dma_len = SPI_INGENIC_FIFO_SIZE;
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ctlr->bits_per_word_mask = pdata->bits_per_word_mask;
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ctlr->min_speed_hz = 7200;
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ctlr->max_speed_hz = pdata->max_speed_hz;
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ctlr->use_gpio_descriptors = true;
|
|
ctlr->max_native_cs = pdata->max_native_cs;
|
|
ctlr->num_chipselect = num_cs;
|
|
ctlr->dev.of_node = pdev->dev.of_node;
|
|
|
|
if (spi_ingenic_request_dma(ctlr, dev))
|
|
dev_warn(dev, "DMA not available.\n");
|
|
|
|
ret = devm_add_action_or_reset(dev, spi_ingenic_release_dma, ctlr);
|
|
if (ret) {
|
|
dev_err(dev, "Unable to add action.\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = devm_spi_register_controller(dev, ctlr);
|
|
if (ret)
|
|
dev_err(dev, "Unable to register SPI controller.\n");
|
|
|
|
return ret;
|
|
}
|
|
|
|
static const struct jz_soc_info jz4750_soc_info = {
|
|
.bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 17),
|
|
.flen_field = REG_FIELD(REG_SSICR1, 4, 7),
|
|
.has_trendian = false,
|
|
|
|
.max_speed_hz = 54000000,
|
|
.max_native_cs = 2,
|
|
};
|
|
|
|
static const struct jz_soc_info jz4780_soc_info = {
|
|
.bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 32),
|
|
.flen_field = REG_FIELD(REG_SSICR1, 3, 7),
|
|
.has_trendian = true,
|
|
|
|
.max_speed_hz = 54000000,
|
|
.max_native_cs = 2,
|
|
};
|
|
|
|
static const struct jz_soc_info x1000_soc_info = {
|
|
.bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 32),
|
|
.flen_field = REG_FIELD(REG_SSICR1, 3, 7),
|
|
.has_trendian = true,
|
|
|
|
.max_speed_hz = 50000000,
|
|
.max_native_cs = 2,
|
|
};
|
|
|
|
static const struct jz_soc_info x2000_soc_info = {
|
|
.bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 32),
|
|
.flen_field = REG_FIELD(REG_SSICR1, 3, 7),
|
|
.has_trendian = true,
|
|
|
|
.max_speed_hz = 50000000,
|
|
.max_native_cs = 1,
|
|
};
|
|
|
|
static const struct of_device_id spi_ingenic_of_match[] = {
|
|
{ .compatible = "ingenic,jz4750-spi", .data = &jz4750_soc_info },
|
|
{ .compatible = "ingenic,jz4775-spi", .data = &jz4780_soc_info },
|
|
{ .compatible = "ingenic,jz4780-spi", .data = &jz4780_soc_info },
|
|
{ .compatible = "ingenic,x1000-spi", .data = &x1000_soc_info },
|
|
{ .compatible = "ingenic,x2000-spi", .data = &x2000_soc_info },
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(of, spi_ingenic_of_match);
|
|
|
|
static struct platform_driver spi_ingenic_driver = {
|
|
.driver = {
|
|
.name = "spi-ingenic",
|
|
.of_match_table = spi_ingenic_of_match,
|
|
},
|
|
.probe = spi_ingenic_probe,
|
|
};
|
|
|
|
module_platform_driver(spi_ingenic_driver);
|
|
MODULE_DESCRIPTION("SPI bus driver for the Ingenic SoCs");
|
|
MODULE_AUTHOR("Artur Rojek <contact@artur-rojek.eu>");
|
|
MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>");
|
|
MODULE_AUTHOR("周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>");
|
|
MODULE_LICENSE("GPL");
|