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![Yangtao Li](/assets/img/avatar_default.png)
Use resource-managed OPP API to simplify code. Signed-off-by: Yangtao Li <tiny.windzz@gmail.com> Acked-by: Mark Brown <broonie@kernel.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
663 lines
16 KiB
C
663 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
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#include <linux/clk.h>
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#include <linux/interconnect.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/pm_runtime.h>
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#include <linux/pm_opp.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/spi-mem.h>
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#define QSPI_NUM_CS 2
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#define QSPI_BYTES_PER_WORD 4
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#define MSTR_CONFIG 0x0000
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#define FULL_CYCLE_MODE BIT(3)
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#define FB_CLK_EN BIT(4)
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#define PIN_HOLDN BIT(6)
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#define PIN_WPN BIT(7)
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#define DMA_ENABLE BIT(8)
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#define BIG_ENDIAN_MODE BIT(9)
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#define SPI_MODE_MSK 0xc00
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#define SPI_MODE_SHFT 10
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#define CHIP_SELECT_NUM BIT(12)
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#define SBL_EN BIT(13)
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#define LPA_BASE_MSK 0x3c000
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#define LPA_BASE_SHFT 14
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#define TX_DATA_DELAY_MSK 0xc0000
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#define TX_DATA_DELAY_SHFT 18
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#define TX_CLK_DELAY_MSK 0x300000
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#define TX_CLK_DELAY_SHFT 20
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#define TX_CS_N_DELAY_MSK 0xc00000
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#define TX_CS_N_DELAY_SHFT 22
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#define TX_DATA_OE_DELAY_MSK 0x3000000
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#define TX_DATA_OE_DELAY_SHFT 24
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#define AHB_MASTER_CFG 0x0004
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#define HMEM_TYPE_START_MID_TRANS_MSK 0x7
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#define HMEM_TYPE_START_MID_TRANS_SHFT 0
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#define HMEM_TYPE_LAST_TRANS_MSK 0x38
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#define HMEM_TYPE_LAST_TRANS_SHFT 3
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#define USE_HMEMTYPE_LAST_ON_DESC_OR_CHAIN_MSK 0xc0
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#define USE_HMEMTYPE_LAST_ON_DESC_OR_CHAIN_SHFT 6
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#define HMEMTYPE_READ_TRANS_MSK 0x700
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#define HMEMTYPE_READ_TRANS_SHFT 8
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#define HSHARED BIT(11)
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#define HINNERSHARED BIT(12)
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#define MSTR_INT_EN 0x000C
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#define MSTR_INT_STATUS 0x0010
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#define RESP_FIFO_UNDERRUN BIT(0)
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#define RESP_FIFO_NOT_EMPTY BIT(1)
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#define RESP_FIFO_RDY BIT(2)
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#define HRESP_FROM_NOC_ERR BIT(3)
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#define WR_FIFO_EMPTY BIT(9)
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#define WR_FIFO_FULL BIT(10)
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#define WR_FIFO_OVERRUN BIT(11)
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#define TRANSACTION_DONE BIT(16)
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#define QSPI_ERR_IRQS (RESP_FIFO_UNDERRUN | HRESP_FROM_NOC_ERR | \
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WR_FIFO_OVERRUN)
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#define QSPI_ALL_IRQS (QSPI_ERR_IRQS | RESP_FIFO_RDY | \
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WR_FIFO_EMPTY | WR_FIFO_FULL | \
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TRANSACTION_DONE)
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#define PIO_XFER_CTRL 0x0014
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#define REQUEST_COUNT_MSK 0xffff
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#define PIO_XFER_CFG 0x0018
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#define TRANSFER_DIRECTION BIT(0)
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#define MULTI_IO_MODE_MSK 0xe
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#define MULTI_IO_MODE_SHFT 1
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#define TRANSFER_FRAGMENT BIT(8)
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#define SDR_1BIT 1
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#define SDR_2BIT 2
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#define SDR_4BIT 3
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#define DDR_1BIT 5
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#define DDR_2BIT 6
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#define DDR_4BIT 7
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#define DMA_DESC_SINGLE_SPI 1
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#define DMA_DESC_DUAL_SPI 2
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#define DMA_DESC_QUAD_SPI 3
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#define PIO_XFER_STATUS 0x001c
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#define WR_FIFO_BYTES_MSK 0xffff0000
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#define WR_FIFO_BYTES_SHFT 16
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#define PIO_DATAOUT_1B 0x0020
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#define PIO_DATAOUT_4B 0x0024
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#define RD_FIFO_CFG 0x0028
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#define CONTINUOUS_MODE BIT(0)
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#define RD_FIFO_STATUS 0x002c
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#define FIFO_EMPTY BIT(11)
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#define WR_CNTS_MSK 0x7f0
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#define WR_CNTS_SHFT 4
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#define RDY_64BYTE BIT(3)
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#define RDY_32BYTE BIT(2)
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#define RDY_16BYTE BIT(1)
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#define FIFO_RDY BIT(0)
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#define RD_FIFO_RESET 0x0030
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#define RESET_FIFO BIT(0)
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#define CUR_MEM_ADDR 0x0048
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#define HW_VERSION 0x004c
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#define RD_FIFO 0x0050
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#define SAMPLING_CLK_CFG 0x0090
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#define SAMPLING_CLK_STATUS 0x0094
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enum qspi_dir {
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QSPI_READ,
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QSPI_WRITE,
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};
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struct qspi_xfer {
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union {
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const void *tx_buf;
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void *rx_buf;
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};
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unsigned int rem_bytes;
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unsigned int buswidth;
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enum qspi_dir dir;
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bool is_last;
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};
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enum qspi_clocks {
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QSPI_CLK_CORE,
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QSPI_CLK_IFACE,
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QSPI_NUM_CLKS
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};
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struct qcom_qspi {
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void __iomem *base;
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struct device *dev;
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struct clk_bulk_data *clks;
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struct qspi_xfer xfer;
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struct icc_path *icc_path_cpu_to_qspi;
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unsigned long last_speed;
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/* Lock to protect data accessed by IRQs */
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spinlock_t lock;
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};
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static u32 qspi_buswidth_to_iomode(struct qcom_qspi *ctrl,
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unsigned int buswidth)
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{
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switch (buswidth) {
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case 1:
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return SDR_1BIT << MULTI_IO_MODE_SHFT;
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case 2:
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return SDR_2BIT << MULTI_IO_MODE_SHFT;
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case 4:
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return SDR_4BIT << MULTI_IO_MODE_SHFT;
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default:
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dev_warn_once(ctrl->dev,
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"Unexpected bus width: %u\n", buswidth);
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return SDR_1BIT << MULTI_IO_MODE_SHFT;
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}
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}
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static void qcom_qspi_pio_xfer_cfg(struct qcom_qspi *ctrl)
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{
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u32 pio_xfer_cfg;
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const struct qspi_xfer *xfer;
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xfer = &ctrl->xfer;
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pio_xfer_cfg = readl(ctrl->base + PIO_XFER_CFG);
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pio_xfer_cfg &= ~TRANSFER_DIRECTION;
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pio_xfer_cfg |= xfer->dir;
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if (xfer->is_last)
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pio_xfer_cfg &= ~TRANSFER_FRAGMENT;
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else
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pio_xfer_cfg |= TRANSFER_FRAGMENT;
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pio_xfer_cfg &= ~MULTI_IO_MODE_MSK;
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pio_xfer_cfg |= qspi_buswidth_to_iomode(ctrl, xfer->buswidth);
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writel(pio_xfer_cfg, ctrl->base + PIO_XFER_CFG);
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}
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static void qcom_qspi_pio_xfer_ctrl(struct qcom_qspi *ctrl)
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{
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u32 pio_xfer_ctrl;
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pio_xfer_ctrl = readl(ctrl->base + PIO_XFER_CTRL);
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pio_xfer_ctrl &= ~REQUEST_COUNT_MSK;
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pio_xfer_ctrl |= ctrl->xfer.rem_bytes;
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writel(pio_xfer_ctrl, ctrl->base + PIO_XFER_CTRL);
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}
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static void qcom_qspi_pio_xfer(struct qcom_qspi *ctrl)
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{
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u32 ints;
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qcom_qspi_pio_xfer_cfg(ctrl);
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/* Ack any previous interrupts that might be hanging around */
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writel(QSPI_ALL_IRQS, ctrl->base + MSTR_INT_STATUS);
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/* Setup new interrupts */
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if (ctrl->xfer.dir == QSPI_WRITE)
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ints = QSPI_ERR_IRQS | WR_FIFO_EMPTY;
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else
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ints = QSPI_ERR_IRQS | RESP_FIFO_RDY;
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writel(ints, ctrl->base + MSTR_INT_EN);
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/* Kick off the transfer */
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qcom_qspi_pio_xfer_ctrl(ctrl);
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}
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static void qcom_qspi_handle_err(struct spi_master *master,
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struct spi_message *msg)
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{
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struct qcom_qspi *ctrl = spi_master_get_devdata(master);
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unsigned long flags;
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spin_lock_irqsave(&ctrl->lock, flags);
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writel(0, ctrl->base + MSTR_INT_EN);
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ctrl->xfer.rem_bytes = 0;
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spin_unlock_irqrestore(&ctrl->lock, flags);
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}
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static int qcom_qspi_set_speed(struct qcom_qspi *ctrl, unsigned long speed_hz)
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{
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int ret;
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unsigned int avg_bw_cpu;
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if (speed_hz == ctrl->last_speed)
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return 0;
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/* In regular operation (SBL_EN=1) core must be 4x transfer clock */
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ret = dev_pm_opp_set_rate(ctrl->dev, speed_hz * 4);
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if (ret) {
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dev_err(ctrl->dev, "Failed to set core clk %d\n", ret);
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return ret;
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}
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/*
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* Set BW quota for CPU as driver supports FIFO mode only.
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* We don't have explicit peak requirement so keep it equal to avg_bw.
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*/
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avg_bw_cpu = Bps_to_icc(speed_hz);
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ret = icc_set_bw(ctrl->icc_path_cpu_to_qspi, avg_bw_cpu, avg_bw_cpu);
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if (ret) {
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dev_err(ctrl->dev, "%s: ICC BW voting failed for cpu: %d\n",
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__func__, ret);
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return ret;
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}
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ctrl->last_speed = speed_hz;
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return 0;
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}
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static int qcom_qspi_transfer_one(struct spi_master *master,
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struct spi_device *slv,
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struct spi_transfer *xfer)
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{
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struct qcom_qspi *ctrl = spi_master_get_devdata(master);
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int ret;
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unsigned long speed_hz;
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unsigned long flags;
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speed_hz = slv->max_speed_hz;
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if (xfer->speed_hz)
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speed_hz = xfer->speed_hz;
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ret = qcom_qspi_set_speed(ctrl, speed_hz);
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if (ret)
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return ret;
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spin_lock_irqsave(&ctrl->lock, flags);
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/* We are half duplex, so either rx or tx will be set */
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if (xfer->rx_buf) {
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ctrl->xfer.dir = QSPI_READ;
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ctrl->xfer.buswidth = xfer->rx_nbits;
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ctrl->xfer.rx_buf = xfer->rx_buf;
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} else {
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ctrl->xfer.dir = QSPI_WRITE;
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ctrl->xfer.buswidth = xfer->tx_nbits;
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ctrl->xfer.tx_buf = xfer->tx_buf;
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}
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ctrl->xfer.is_last = list_is_last(&xfer->transfer_list,
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&master->cur_msg->transfers);
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ctrl->xfer.rem_bytes = xfer->len;
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qcom_qspi_pio_xfer(ctrl);
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spin_unlock_irqrestore(&ctrl->lock, flags);
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/* We'll call spi_finalize_current_transfer() when done */
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return 1;
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}
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static int qcom_qspi_prepare_message(struct spi_master *master,
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struct spi_message *message)
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{
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u32 mstr_cfg;
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struct qcom_qspi *ctrl;
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int tx_data_oe_delay = 1;
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int tx_data_delay = 1;
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unsigned long flags;
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ctrl = spi_master_get_devdata(master);
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spin_lock_irqsave(&ctrl->lock, flags);
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mstr_cfg = readl(ctrl->base + MSTR_CONFIG);
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mstr_cfg &= ~CHIP_SELECT_NUM;
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if (message->spi->chip_select)
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mstr_cfg |= CHIP_SELECT_NUM;
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mstr_cfg |= FB_CLK_EN | PIN_WPN | PIN_HOLDN | SBL_EN | FULL_CYCLE_MODE;
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mstr_cfg &= ~(SPI_MODE_MSK | TX_DATA_OE_DELAY_MSK | TX_DATA_DELAY_MSK);
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mstr_cfg |= message->spi->mode << SPI_MODE_SHFT;
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mstr_cfg |= tx_data_oe_delay << TX_DATA_OE_DELAY_SHFT;
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mstr_cfg |= tx_data_delay << TX_DATA_DELAY_SHFT;
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mstr_cfg &= ~DMA_ENABLE;
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writel(mstr_cfg, ctrl->base + MSTR_CONFIG);
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spin_unlock_irqrestore(&ctrl->lock, flags);
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return 0;
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}
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static irqreturn_t pio_read(struct qcom_qspi *ctrl)
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{
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u32 rd_fifo_status;
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u32 rd_fifo;
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unsigned int wr_cnts;
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unsigned int bytes_to_read;
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unsigned int words_to_read;
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u32 *word_buf;
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u8 *byte_buf;
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int i;
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rd_fifo_status = readl(ctrl->base + RD_FIFO_STATUS);
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if (!(rd_fifo_status & FIFO_RDY)) {
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dev_dbg(ctrl->dev, "Spurious IRQ %#x\n", rd_fifo_status);
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return IRQ_NONE;
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}
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wr_cnts = (rd_fifo_status & WR_CNTS_MSK) >> WR_CNTS_SHFT;
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wr_cnts = min(wr_cnts, ctrl->xfer.rem_bytes);
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words_to_read = wr_cnts / QSPI_BYTES_PER_WORD;
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bytes_to_read = wr_cnts % QSPI_BYTES_PER_WORD;
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if (words_to_read) {
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word_buf = ctrl->xfer.rx_buf;
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ctrl->xfer.rem_bytes -= words_to_read * QSPI_BYTES_PER_WORD;
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ioread32_rep(ctrl->base + RD_FIFO, word_buf, words_to_read);
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ctrl->xfer.rx_buf = word_buf + words_to_read;
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}
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if (bytes_to_read) {
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byte_buf = ctrl->xfer.rx_buf;
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rd_fifo = readl(ctrl->base + RD_FIFO);
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ctrl->xfer.rem_bytes -= bytes_to_read;
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for (i = 0; i < bytes_to_read; i++)
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*byte_buf++ = rd_fifo >> (i * BITS_PER_BYTE);
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ctrl->xfer.rx_buf = byte_buf;
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}
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return IRQ_HANDLED;
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}
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static irqreturn_t pio_write(struct qcom_qspi *ctrl)
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{
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const void *xfer_buf = ctrl->xfer.tx_buf;
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const int *word_buf;
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const char *byte_buf;
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unsigned int wr_fifo_bytes;
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unsigned int wr_fifo_words;
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unsigned int wr_size;
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unsigned int rem_words;
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wr_fifo_bytes = readl(ctrl->base + PIO_XFER_STATUS);
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wr_fifo_bytes >>= WR_FIFO_BYTES_SHFT;
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if (ctrl->xfer.rem_bytes < QSPI_BYTES_PER_WORD) {
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/* Process the last 1-3 bytes */
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wr_size = min(wr_fifo_bytes, ctrl->xfer.rem_bytes);
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ctrl->xfer.rem_bytes -= wr_size;
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byte_buf = xfer_buf;
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while (wr_size--)
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writel(*byte_buf++,
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ctrl->base + PIO_DATAOUT_1B);
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ctrl->xfer.tx_buf = byte_buf;
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} else {
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/*
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* Process all the whole words; to keep things simple we'll
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* just wait for the next interrupt to handle the last 1-3
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* bytes if we don't have an even number of words.
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*/
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rem_words = ctrl->xfer.rem_bytes / QSPI_BYTES_PER_WORD;
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wr_fifo_words = wr_fifo_bytes / QSPI_BYTES_PER_WORD;
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wr_size = min(rem_words, wr_fifo_words);
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ctrl->xfer.rem_bytes -= wr_size * QSPI_BYTES_PER_WORD;
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word_buf = xfer_buf;
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iowrite32_rep(ctrl->base + PIO_DATAOUT_4B, word_buf, wr_size);
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ctrl->xfer.tx_buf = word_buf + wr_size;
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}
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return IRQ_HANDLED;
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}
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static irqreturn_t qcom_qspi_irq(int irq, void *dev_id)
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{
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u32 int_status;
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struct qcom_qspi *ctrl = dev_id;
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irqreturn_t ret = IRQ_NONE;
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spin_lock(&ctrl->lock);
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int_status = readl(ctrl->base + MSTR_INT_STATUS);
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writel(int_status, ctrl->base + MSTR_INT_STATUS);
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if (ctrl->xfer.dir == QSPI_WRITE) {
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if (int_status & WR_FIFO_EMPTY)
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ret = pio_write(ctrl);
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} else {
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if (int_status & RESP_FIFO_RDY)
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ret = pio_read(ctrl);
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}
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if (int_status & QSPI_ERR_IRQS) {
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if (int_status & RESP_FIFO_UNDERRUN)
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dev_err(ctrl->dev, "IRQ error: FIFO underrun\n");
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if (int_status & WR_FIFO_OVERRUN)
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dev_err(ctrl->dev, "IRQ error: FIFO overrun\n");
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if (int_status & HRESP_FROM_NOC_ERR)
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dev_err(ctrl->dev, "IRQ error: NOC response error\n");
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ret = IRQ_HANDLED;
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}
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if (!ctrl->xfer.rem_bytes) {
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writel(0, ctrl->base + MSTR_INT_EN);
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spi_finalize_current_transfer(dev_get_drvdata(ctrl->dev));
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}
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spin_unlock(&ctrl->lock);
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return ret;
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}
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static int qcom_qspi_probe(struct platform_device *pdev)
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{
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int ret;
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struct device *dev;
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struct spi_master *master;
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struct qcom_qspi *ctrl;
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dev = &pdev->dev;
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master = devm_spi_alloc_master(dev, sizeof(*ctrl));
|
|
if (!master)
|
|
return -ENOMEM;
|
|
|
|
platform_set_drvdata(pdev, master);
|
|
|
|
ctrl = spi_master_get_devdata(master);
|
|
|
|
spin_lock_init(&ctrl->lock);
|
|
ctrl->dev = dev;
|
|
ctrl->base = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(ctrl->base))
|
|
return PTR_ERR(ctrl->base);
|
|
|
|
ctrl->clks = devm_kcalloc(dev, QSPI_NUM_CLKS,
|
|
sizeof(*ctrl->clks), GFP_KERNEL);
|
|
if (!ctrl->clks)
|
|
return -ENOMEM;
|
|
|
|
ctrl->clks[QSPI_CLK_CORE].id = "core";
|
|
ctrl->clks[QSPI_CLK_IFACE].id = "iface";
|
|
ret = devm_clk_bulk_get(dev, QSPI_NUM_CLKS, ctrl->clks);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ctrl->icc_path_cpu_to_qspi = devm_of_icc_get(dev, "qspi-config");
|
|
if (IS_ERR(ctrl->icc_path_cpu_to_qspi))
|
|
return dev_err_probe(dev, PTR_ERR(ctrl->icc_path_cpu_to_qspi),
|
|
"Failed to get cpu path\n");
|
|
|
|
/* Set BW vote for register access */
|
|
ret = icc_set_bw(ctrl->icc_path_cpu_to_qspi, Bps_to_icc(1000),
|
|
Bps_to_icc(1000));
|
|
if (ret) {
|
|
dev_err(ctrl->dev, "%s: ICC BW voting failed for cpu: %d\n",
|
|
__func__, ret);
|
|
return ret;
|
|
}
|
|
|
|
ret = icc_disable(ctrl->icc_path_cpu_to_qspi);
|
|
if (ret) {
|
|
dev_err(ctrl->dev, "%s: ICC disable failed for cpu: %d\n",
|
|
__func__, ret);
|
|
return ret;
|
|
}
|
|
|
|
ret = platform_get_irq(pdev, 0);
|
|
if (ret < 0)
|
|
return ret;
|
|
ret = devm_request_irq(dev, ret, qcom_qspi_irq, 0, dev_name(dev), ctrl);
|
|
if (ret) {
|
|
dev_err(dev, "Failed to request irq %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
master->max_speed_hz = 300000000;
|
|
master->num_chipselect = QSPI_NUM_CS;
|
|
master->bus_num = -1;
|
|
master->dev.of_node = pdev->dev.of_node;
|
|
master->mode_bits = SPI_MODE_0 |
|
|
SPI_TX_DUAL | SPI_RX_DUAL |
|
|
SPI_TX_QUAD | SPI_RX_QUAD;
|
|
master->flags = SPI_MASTER_HALF_DUPLEX;
|
|
master->prepare_message = qcom_qspi_prepare_message;
|
|
master->transfer_one = qcom_qspi_transfer_one;
|
|
master->handle_err = qcom_qspi_handle_err;
|
|
master->auto_runtime_pm = true;
|
|
|
|
ret = devm_pm_opp_set_clkname(&pdev->dev, "core");
|
|
if (ret)
|
|
return ret;
|
|
/* OPP table is optional */
|
|
ret = devm_pm_opp_of_add_table(&pdev->dev);
|
|
if (ret && ret != -ENODEV) {
|
|
dev_err(&pdev->dev, "invalid OPP table in device tree\n");
|
|
return ret;
|
|
}
|
|
|
|
pm_runtime_use_autosuspend(dev);
|
|
pm_runtime_set_autosuspend_delay(dev, 250);
|
|
pm_runtime_enable(dev);
|
|
|
|
ret = spi_register_master(master);
|
|
if (!ret)
|
|
return 0;
|
|
|
|
pm_runtime_disable(dev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int qcom_qspi_remove(struct platform_device *pdev)
|
|
{
|
|
struct spi_master *master = platform_get_drvdata(pdev);
|
|
|
|
/* Unregister _before_ disabling pm_runtime() so we stop transfers */
|
|
spi_unregister_master(master);
|
|
|
|
pm_runtime_disable(&pdev->dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused qcom_qspi_runtime_suspend(struct device *dev)
|
|
{
|
|
struct spi_master *master = dev_get_drvdata(dev);
|
|
struct qcom_qspi *ctrl = spi_master_get_devdata(master);
|
|
int ret;
|
|
|
|
/* Drop the performance state vote */
|
|
dev_pm_opp_set_rate(dev, 0);
|
|
clk_bulk_disable_unprepare(QSPI_NUM_CLKS, ctrl->clks);
|
|
|
|
ret = icc_disable(ctrl->icc_path_cpu_to_qspi);
|
|
if (ret) {
|
|
dev_err_ratelimited(ctrl->dev, "%s: ICC disable failed for cpu: %d\n",
|
|
__func__, ret);
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused qcom_qspi_runtime_resume(struct device *dev)
|
|
{
|
|
struct spi_master *master = dev_get_drvdata(dev);
|
|
struct qcom_qspi *ctrl = spi_master_get_devdata(master);
|
|
int ret;
|
|
|
|
ret = icc_enable(ctrl->icc_path_cpu_to_qspi);
|
|
if (ret) {
|
|
dev_err_ratelimited(ctrl->dev, "%s: ICC enable failed for cpu: %d\n",
|
|
__func__, ret);
|
|
return ret;
|
|
}
|
|
|
|
ret = clk_bulk_prepare_enable(QSPI_NUM_CLKS, ctrl->clks);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return dev_pm_opp_set_rate(dev, ctrl->last_speed * 4);
|
|
}
|
|
|
|
static int __maybe_unused qcom_qspi_suspend(struct device *dev)
|
|
{
|
|
struct spi_master *master = dev_get_drvdata(dev);
|
|
int ret;
|
|
|
|
ret = spi_master_suspend(master);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = pm_runtime_force_suspend(dev);
|
|
if (ret)
|
|
spi_master_resume(master);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int __maybe_unused qcom_qspi_resume(struct device *dev)
|
|
{
|
|
struct spi_master *master = dev_get_drvdata(dev);
|
|
int ret;
|
|
|
|
ret = pm_runtime_force_resume(dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = spi_master_resume(master);
|
|
if (ret)
|
|
pm_runtime_force_suspend(dev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static const struct dev_pm_ops qcom_qspi_dev_pm_ops = {
|
|
SET_RUNTIME_PM_OPS(qcom_qspi_runtime_suspend,
|
|
qcom_qspi_runtime_resume, NULL)
|
|
SET_SYSTEM_SLEEP_PM_OPS(qcom_qspi_suspend, qcom_qspi_resume)
|
|
};
|
|
|
|
static const struct of_device_id qcom_qspi_dt_match[] = {
|
|
{ .compatible = "qcom,qspi-v1", },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, qcom_qspi_dt_match);
|
|
|
|
static struct platform_driver qcom_qspi_driver = {
|
|
.driver = {
|
|
.name = "qcom_qspi",
|
|
.pm = &qcom_qspi_dev_pm_ops,
|
|
.of_match_table = qcom_qspi_dt_match,
|
|
},
|
|
.probe = qcom_qspi_probe,
|
|
.remove = qcom_qspi_remove,
|
|
};
|
|
module_platform_driver(qcom_qspi_driver);
|
|
|
|
MODULE_DESCRIPTION("SPI driver for QSPI cores");
|
|
MODULE_LICENSE("GPL v2");
|