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![David S. Miller](/assets/img/avatar_default.png)
Changeset fde6a3c82d
("iommu sg merging:
sparc64: make iommu respect the segment size limits") broke sparc64
because whilst it added the segment limiting code to the first pass of
SG mapping (in prepare_sg()) it did not add matching code to the
second pass handling (in fill_sg())
As a result the two passes disagree where the segment boundaries
should be, resulting in OOPSes, DMA corruption, and corrupted
superblocks.
Signed-off-by: David S. Miller <davem@davemloft.net>
726 lines
17 KiB
C
726 lines
17 KiB
C
/* iommu.c: Generic sparc64 IOMMU support.
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*
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* Copyright (C) 1999, 2007 David S. Miller (davem@davemloft.net)
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* Copyright (C) 1999, 2000 Jakub Jelinek (jakub@redhat.com)
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/dma-mapping.h>
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#include <linux/errno.h>
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#ifdef CONFIG_PCI
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#include <linux/pci.h>
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#endif
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#include <asm/iommu.h>
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#include "iommu_common.h"
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#define STC_CTXMATCH_ADDR(STC, CTX) \
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((STC)->strbuf_ctxmatch_base + ((CTX) << 3))
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#define STC_FLUSHFLAG_INIT(STC) \
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(*((STC)->strbuf_flushflag) = 0UL)
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#define STC_FLUSHFLAG_SET(STC) \
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(*((STC)->strbuf_flushflag) != 0UL)
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#define iommu_read(__reg) \
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({ u64 __ret; \
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__asm__ __volatile__("ldxa [%1] %2, %0" \
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: "=r" (__ret) \
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: "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
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: "memory"); \
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__ret; \
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})
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#define iommu_write(__reg, __val) \
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__asm__ __volatile__("stxa %0, [%1] %2" \
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: /* no outputs */ \
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: "r" (__val), "r" (__reg), \
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"i" (ASI_PHYS_BYPASS_EC_E))
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/* Must be invoked under the IOMMU lock. */
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static void __iommu_flushall(struct iommu *iommu)
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{
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if (iommu->iommu_flushinv) {
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iommu_write(iommu->iommu_flushinv, ~(u64)0);
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} else {
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unsigned long tag;
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int entry;
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tag = iommu->iommu_tags;
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for (entry = 0; entry < 16; entry++) {
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iommu_write(tag, 0);
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tag += 8;
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}
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/* Ensure completion of previous PIO writes. */
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(void) iommu_read(iommu->write_complete_reg);
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}
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}
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#define IOPTE_CONSISTENT(CTX) \
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(IOPTE_VALID | IOPTE_CACHE | \
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(((CTX) << 47) & IOPTE_CONTEXT))
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#define IOPTE_STREAMING(CTX) \
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(IOPTE_CONSISTENT(CTX) | IOPTE_STBUF)
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/* Existing mappings are never marked invalid, instead they
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* are pointed to a dummy page.
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*/
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#define IOPTE_IS_DUMMY(iommu, iopte) \
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((iopte_val(*iopte) & IOPTE_PAGE) == (iommu)->dummy_page_pa)
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static inline void iopte_make_dummy(struct iommu *iommu, iopte_t *iopte)
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{
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unsigned long val = iopte_val(*iopte);
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val &= ~IOPTE_PAGE;
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val |= iommu->dummy_page_pa;
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iopte_val(*iopte) = val;
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}
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/* Based largely upon the ppc64 iommu allocator. */
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static long arena_alloc(struct iommu *iommu, unsigned long npages)
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{
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struct iommu_arena *arena = &iommu->arena;
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unsigned long n, i, start, end, limit;
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int pass;
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limit = arena->limit;
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start = arena->hint;
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pass = 0;
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again:
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n = find_next_zero_bit(arena->map, limit, start);
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end = n + npages;
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if (unlikely(end >= limit)) {
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if (likely(pass < 1)) {
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limit = start;
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start = 0;
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__iommu_flushall(iommu);
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pass++;
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goto again;
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} else {
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/* Scanned the whole thing, give up. */
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return -1;
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}
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}
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for (i = n; i < end; i++) {
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if (test_bit(i, arena->map)) {
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start = i + 1;
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goto again;
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}
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}
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for (i = n; i < end; i++)
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__set_bit(i, arena->map);
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arena->hint = end;
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return n;
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}
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static void arena_free(struct iommu_arena *arena, unsigned long base, unsigned long npages)
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{
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unsigned long i;
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for (i = base; i < (base + npages); i++)
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__clear_bit(i, arena->map);
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}
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int iommu_table_init(struct iommu *iommu, int tsbsize,
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u32 dma_offset, u32 dma_addr_mask)
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{
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unsigned long i, tsbbase, order, sz, num_tsb_entries;
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num_tsb_entries = tsbsize / sizeof(iopte_t);
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/* Setup initial software IOMMU state. */
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spin_lock_init(&iommu->lock);
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iommu->ctx_lowest_free = 1;
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iommu->page_table_map_base = dma_offset;
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iommu->dma_addr_mask = dma_addr_mask;
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/* Allocate and initialize the free area map. */
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sz = num_tsb_entries / 8;
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sz = (sz + 7UL) & ~7UL;
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iommu->arena.map = kzalloc(sz, GFP_KERNEL);
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if (!iommu->arena.map) {
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printk(KERN_ERR "IOMMU: Error, kmalloc(arena.map) failed.\n");
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return -ENOMEM;
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}
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iommu->arena.limit = num_tsb_entries;
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/* Allocate and initialize the dummy page which we
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* set inactive IO PTEs to point to.
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*/
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iommu->dummy_page = __get_free_pages(GFP_KERNEL, 0);
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if (!iommu->dummy_page) {
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printk(KERN_ERR "IOMMU: Error, gfp(dummy_page) failed.\n");
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goto out_free_map;
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}
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memset((void *)iommu->dummy_page, 0, PAGE_SIZE);
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iommu->dummy_page_pa = (unsigned long) __pa(iommu->dummy_page);
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/* Now allocate and setup the IOMMU page table itself. */
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order = get_order(tsbsize);
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tsbbase = __get_free_pages(GFP_KERNEL, order);
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if (!tsbbase) {
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printk(KERN_ERR "IOMMU: Error, gfp(tsb) failed.\n");
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goto out_free_dummy_page;
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}
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iommu->page_table = (iopte_t *)tsbbase;
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for (i = 0; i < num_tsb_entries; i++)
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iopte_make_dummy(iommu, &iommu->page_table[i]);
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return 0;
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out_free_dummy_page:
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free_page(iommu->dummy_page);
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iommu->dummy_page = 0UL;
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out_free_map:
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kfree(iommu->arena.map);
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iommu->arena.map = NULL;
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return -ENOMEM;
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}
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static inline iopte_t *alloc_npages(struct iommu *iommu, unsigned long npages)
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{
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long entry;
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entry = arena_alloc(iommu, npages);
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if (unlikely(entry < 0))
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return NULL;
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return iommu->page_table + entry;
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}
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static inline void free_npages(struct iommu *iommu, dma_addr_t base, unsigned long npages)
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{
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arena_free(&iommu->arena, base >> IO_PAGE_SHIFT, npages);
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}
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static int iommu_alloc_ctx(struct iommu *iommu)
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{
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int lowest = iommu->ctx_lowest_free;
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int sz = IOMMU_NUM_CTXS - lowest;
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int n = find_next_zero_bit(iommu->ctx_bitmap, sz, lowest);
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if (unlikely(n == sz)) {
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n = find_next_zero_bit(iommu->ctx_bitmap, lowest, 1);
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if (unlikely(n == lowest)) {
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printk(KERN_WARNING "IOMMU: Ran out of contexts.\n");
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n = 0;
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}
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}
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if (n)
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__set_bit(n, iommu->ctx_bitmap);
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return n;
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}
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static inline void iommu_free_ctx(struct iommu *iommu, int ctx)
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{
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if (likely(ctx)) {
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__clear_bit(ctx, iommu->ctx_bitmap);
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if (ctx < iommu->ctx_lowest_free)
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iommu->ctx_lowest_free = ctx;
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}
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}
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static void *dma_4u_alloc_coherent(struct device *dev, size_t size,
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dma_addr_t *dma_addrp, gfp_t gfp)
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{
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struct iommu *iommu;
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iopte_t *iopte;
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unsigned long flags, order, first_page;
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void *ret;
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int npages;
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size = IO_PAGE_ALIGN(size);
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order = get_order(size);
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if (order >= 10)
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return NULL;
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first_page = __get_free_pages(gfp, order);
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if (first_page == 0UL)
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return NULL;
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memset((char *)first_page, 0, PAGE_SIZE << order);
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iommu = dev->archdata.iommu;
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spin_lock_irqsave(&iommu->lock, flags);
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iopte = alloc_npages(iommu, size >> IO_PAGE_SHIFT);
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spin_unlock_irqrestore(&iommu->lock, flags);
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if (unlikely(iopte == NULL)) {
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free_pages(first_page, order);
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return NULL;
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}
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*dma_addrp = (iommu->page_table_map_base +
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((iopte - iommu->page_table) << IO_PAGE_SHIFT));
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ret = (void *) first_page;
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npages = size >> IO_PAGE_SHIFT;
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first_page = __pa(first_page);
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while (npages--) {
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iopte_val(*iopte) = (IOPTE_CONSISTENT(0UL) |
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IOPTE_WRITE |
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(first_page & IOPTE_PAGE));
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iopte++;
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first_page += IO_PAGE_SIZE;
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}
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return ret;
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}
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static void dma_4u_free_coherent(struct device *dev, size_t size,
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void *cpu, dma_addr_t dvma)
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{
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struct iommu *iommu;
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iopte_t *iopte;
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unsigned long flags, order, npages;
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npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;
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iommu = dev->archdata.iommu;
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iopte = iommu->page_table +
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((dvma - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
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spin_lock_irqsave(&iommu->lock, flags);
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free_npages(iommu, dvma - iommu->page_table_map_base, npages);
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spin_unlock_irqrestore(&iommu->lock, flags);
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order = get_order(size);
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if (order < 10)
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free_pages((unsigned long)cpu, order);
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}
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static dma_addr_t dma_4u_map_single(struct device *dev, void *ptr, size_t sz,
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enum dma_data_direction direction)
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{
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struct iommu *iommu;
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struct strbuf *strbuf;
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iopte_t *base;
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unsigned long flags, npages, oaddr;
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unsigned long i, base_paddr, ctx;
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u32 bus_addr, ret;
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unsigned long iopte_protection;
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iommu = dev->archdata.iommu;
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strbuf = dev->archdata.stc;
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if (unlikely(direction == DMA_NONE))
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goto bad_no_ctx;
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oaddr = (unsigned long)ptr;
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npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK);
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npages >>= IO_PAGE_SHIFT;
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spin_lock_irqsave(&iommu->lock, flags);
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base = alloc_npages(iommu, npages);
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ctx = 0;
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if (iommu->iommu_ctxflush)
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ctx = iommu_alloc_ctx(iommu);
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spin_unlock_irqrestore(&iommu->lock, flags);
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if (unlikely(!base))
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goto bad;
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bus_addr = (iommu->page_table_map_base +
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((base - iommu->page_table) << IO_PAGE_SHIFT));
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ret = bus_addr | (oaddr & ~IO_PAGE_MASK);
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base_paddr = __pa(oaddr & IO_PAGE_MASK);
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if (strbuf->strbuf_enabled)
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iopte_protection = IOPTE_STREAMING(ctx);
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else
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iopte_protection = IOPTE_CONSISTENT(ctx);
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if (direction != DMA_TO_DEVICE)
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iopte_protection |= IOPTE_WRITE;
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for (i = 0; i < npages; i++, base++, base_paddr += IO_PAGE_SIZE)
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iopte_val(*base) = iopte_protection | base_paddr;
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return ret;
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bad:
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iommu_free_ctx(iommu, ctx);
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bad_no_ctx:
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if (printk_ratelimit())
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WARN_ON(1);
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return DMA_ERROR_CODE;
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}
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static void strbuf_flush(struct strbuf *strbuf, struct iommu *iommu,
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u32 vaddr, unsigned long ctx, unsigned long npages,
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enum dma_data_direction direction)
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{
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int limit;
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if (strbuf->strbuf_ctxflush &&
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iommu->iommu_ctxflush) {
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unsigned long matchreg, flushreg;
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u64 val;
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flushreg = strbuf->strbuf_ctxflush;
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matchreg = STC_CTXMATCH_ADDR(strbuf, ctx);
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iommu_write(flushreg, ctx);
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val = iommu_read(matchreg);
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val &= 0xffff;
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if (!val)
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goto do_flush_sync;
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while (val) {
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if (val & 0x1)
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iommu_write(flushreg, ctx);
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val >>= 1;
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}
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val = iommu_read(matchreg);
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if (unlikely(val)) {
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printk(KERN_WARNING "strbuf_flush: ctx flush "
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"timeout matchreg[%lx] ctx[%lx]\n",
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val, ctx);
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goto do_page_flush;
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}
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} else {
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unsigned long i;
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do_page_flush:
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for (i = 0; i < npages; i++, vaddr += IO_PAGE_SIZE)
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iommu_write(strbuf->strbuf_pflush, vaddr);
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}
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do_flush_sync:
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/* If the device could not have possibly put dirty data into
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* the streaming cache, no flush-flag synchronization needs
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* to be performed.
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*/
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if (direction == DMA_TO_DEVICE)
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return;
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STC_FLUSHFLAG_INIT(strbuf);
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iommu_write(strbuf->strbuf_fsync, strbuf->strbuf_flushflag_pa);
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(void) iommu_read(iommu->write_complete_reg);
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limit = 100000;
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while (!STC_FLUSHFLAG_SET(strbuf)) {
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limit--;
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if (!limit)
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break;
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udelay(1);
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rmb();
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}
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if (!limit)
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printk(KERN_WARNING "strbuf_flush: flushflag timeout "
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"vaddr[%08x] ctx[%lx] npages[%ld]\n",
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vaddr, ctx, npages);
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}
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static void dma_4u_unmap_single(struct device *dev, dma_addr_t bus_addr,
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size_t sz, enum dma_data_direction direction)
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{
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struct iommu *iommu;
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struct strbuf *strbuf;
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iopte_t *base;
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unsigned long flags, npages, ctx, i;
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if (unlikely(direction == DMA_NONE)) {
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if (printk_ratelimit())
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WARN_ON(1);
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return;
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}
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iommu = dev->archdata.iommu;
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strbuf = dev->archdata.stc;
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npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
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npages >>= IO_PAGE_SHIFT;
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base = iommu->page_table +
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((bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
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bus_addr &= IO_PAGE_MASK;
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spin_lock_irqsave(&iommu->lock, flags);
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/* Record the context, if any. */
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ctx = 0;
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if (iommu->iommu_ctxflush)
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ctx = (iopte_val(*base) & IOPTE_CONTEXT) >> 47UL;
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/* Step 1: Kick data out of streaming buffers if necessary. */
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if (strbuf->strbuf_enabled)
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strbuf_flush(strbuf, iommu, bus_addr, ctx,
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npages, direction);
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/* Step 2: Clear out TSB entries. */
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for (i = 0; i < npages; i++)
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iopte_make_dummy(iommu, base + i);
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free_npages(iommu, bus_addr - iommu->page_table_map_base, npages);
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iommu_free_ctx(iommu, ctx);
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spin_unlock_irqrestore(&iommu->lock, flags);
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}
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static int dma_4u_map_sg(struct device *dev, struct scatterlist *sglist,
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int nelems, enum dma_data_direction direction)
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{
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unsigned long flags, ctx, i, npages, iopte_protection;
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struct scatterlist *sg;
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struct strbuf *strbuf;
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struct iommu *iommu;
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iopte_t *base;
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u32 dma_base;
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/* Fast path single entry scatterlists. */
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if (nelems == 1) {
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sglist->dma_address =
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dma_4u_map_single(dev, sg_virt(sglist),
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sglist->length, direction);
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if (unlikely(sglist->dma_address == DMA_ERROR_CODE))
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return 0;
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sglist->dma_length = sglist->length;
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return 1;
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}
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iommu = dev->archdata.iommu;
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strbuf = dev->archdata.stc;
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if (unlikely(direction == DMA_NONE))
|
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goto bad_no_ctx;
|
|
|
|
npages = calc_npages(sglist, nelems);
|
|
|
|
spin_lock_irqsave(&iommu->lock, flags);
|
|
|
|
base = alloc_npages(iommu, npages);
|
|
ctx = 0;
|
|
if (iommu->iommu_ctxflush)
|
|
ctx = iommu_alloc_ctx(iommu);
|
|
|
|
spin_unlock_irqrestore(&iommu->lock, flags);
|
|
|
|
if (base == NULL)
|
|
goto bad;
|
|
|
|
dma_base = iommu->page_table_map_base +
|
|
((base - iommu->page_table) << IO_PAGE_SHIFT);
|
|
|
|
if (strbuf->strbuf_enabled)
|
|
iopte_protection = IOPTE_STREAMING(ctx);
|
|
else
|
|
iopte_protection = IOPTE_CONSISTENT(ctx);
|
|
if (direction != DMA_TO_DEVICE)
|
|
iopte_protection |= IOPTE_WRITE;
|
|
|
|
for_each_sg(sglist, sg, nelems, i) {
|
|
unsigned long paddr = SG_ENT_PHYS_ADDRESS(sg);
|
|
unsigned long slen = sg->length;
|
|
unsigned long this_npages;
|
|
|
|
this_npages = iommu_num_pages(paddr, slen);
|
|
|
|
sg->dma_address = dma_base | (paddr & ~IO_PAGE_MASK);
|
|
sg->dma_length = slen;
|
|
|
|
paddr &= IO_PAGE_MASK;
|
|
while (this_npages--) {
|
|
iopte_val(*base) = iopte_protection | paddr;
|
|
|
|
base++;
|
|
paddr += IO_PAGE_SIZE;
|
|
dma_base += IO_PAGE_SIZE;
|
|
}
|
|
}
|
|
|
|
return nelems;
|
|
|
|
bad:
|
|
iommu_free_ctx(iommu, ctx);
|
|
bad_no_ctx:
|
|
if (printk_ratelimit())
|
|
WARN_ON(1);
|
|
return 0;
|
|
}
|
|
|
|
static void dma_4u_unmap_sg(struct device *dev, struct scatterlist *sglist,
|
|
int nelems, enum dma_data_direction direction)
|
|
{
|
|
unsigned long flags, ctx, i, npages;
|
|
struct strbuf *strbuf;
|
|
struct iommu *iommu;
|
|
iopte_t *base;
|
|
u32 bus_addr;
|
|
|
|
if (unlikely(direction == DMA_NONE)) {
|
|
if (printk_ratelimit())
|
|
WARN_ON(1);
|
|
}
|
|
|
|
iommu = dev->archdata.iommu;
|
|
strbuf = dev->archdata.stc;
|
|
|
|
bus_addr = sglist->dma_address & IO_PAGE_MASK;
|
|
|
|
npages = calc_npages(sglist, nelems);
|
|
|
|
base = iommu->page_table +
|
|
((bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
|
|
|
|
spin_lock_irqsave(&iommu->lock, flags);
|
|
|
|
/* Record the context, if any. */
|
|
ctx = 0;
|
|
if (iommu->iommu_ctxflush)
|
|
ctx = (iopte_val(*base) & IOPTE_CONTEXT) >> 47UL;
|
|
|
|
/* Step 1: Kick data out of streaming buffers if necessary. */
|
|
if (strbuf->strbuf_enabled)
|
|
strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, direction);
|
|
|
|
/* Step 2: Clear out the TSB entries. */
|
|
for (i = 0; i < npages; i++)
|
|
iopte_make_dummy(iommu, base + i);
|
|
|
|
free_npages(iommu, bus_addr - iommu->page_table_map_base, npages);
|
|
|
|
iommu_free_ctx(iommu, ctx);
|
|
|
|
spin_unlock_irqrestore(&iommu->lock, flags);
|
|
}
|
|
|
|
static void dma_4u_sync_single_for_cpu(struct device *dev,
|
|
dma_addr_t bus_addr, size_t sz,
|
|
enum dma_data_direction direction)
|
|
{
|
|
struct iommu *iommu;
|
|
struct strbuf *strbuf;
|
|
unsigned long flags, ctx, npages;
|
|
|
|
iommu = dev->archdata.iommu;
|
|
strbuf = dev->archdata.stc;
|
|
|
|
if (!strbuf->strbuf_enabled)
|
|
return;
|
|
|
|
spin_lock_irqsave(&iommu->lock, flags);
|
|
|
|
npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
|
|
npages >>= IO_PAGE_SHIFT;
|
|
bus_addr &= IO_PAGE_MASK;
|
|
|
|
/* Step 1: Record the context, if any. */
|
|
ctx = 0;
|
|
if (iommu->iommu_ctxflush &&
|
|
strbuf->strbuf_ctxflush) {
|
|
iopte_t *iopte;
|
|
|
|
iopte = iommu->page_table +
|
|
((bus_addr - iommu->page_table_map_base)>>IO_PAGE_SHIFT);
|
|
ctx = (iopte_val(*iopte) & IOPTE_CONTEXT) >> 47UL;
|
|
}
|
|
|
|
/* Step 2: Kick data out of streaming buffers. */
|
|
strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, direction);
|
|
|
|
spin_unlock_irqrestore(&iommu->lock, flags);
|
|
}
|
|
|
|
static void dma_4u_sync_sg_for_cpu(struct device *dev,
|
|
struct scatterlist *sglist, int nelems,
|
|
enum dma_data_direction direction)
|
|
{
|
|
struct iommu *iommu;
|
|
struct strbuf *strbuf;
|
|
unsigned long flags, ctx, npages, i;
|
|
struct scatterlist *sg, *sgprv;
|
|
u32 bus_addr;
|
|
|
|
iommu = dev->archdata.iommu;
|
|
strbuf = dev->archdata.stc;
|
|
|
|
if (!strbuf->strbuf_enabled)
|
|
return;
|
|
|
|
spin_lock_irqsave(&iommu->lock, flags);
|
|
|
|
/* Step 1: Record the context, if any. */
|
|
ctx = 0;
|
|
if (iommu->iommu_ctxflush &&
|
|
strbuf->strbuf_ctxflush) {
|
|
iopte_t *iopte;
|
|
|
|
iopte = iommu->page_table +
|
|
((sglist[0].dma_address - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
|
|
ctx = (iopte_val(*iopte) & IOPTE_CONTEXT) >> 47UL;
|
|
}
|
|
|
|
/* Step 2: Kick data out of streaming buffers. */
|
|
bus_addr = sglist[0].dma_address & IO_PAGE_MASK;
|
|
sgprv = NULL;
|
|
for_each_sg(sglist, sg, nelems, i) {
|
|
if (sg->dma_length == 0)
|
|
break;
|
|
sgprv = sg;
|
|
}
|
|
|
|
npages = (IO_PAGE_ALIGN(sgprv->dma_address + sgprv->dma_length)
|
|
- bus_addr) >> IO_PAGE_SHIFT;
|
|
strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, direction);
|
|
|
|
spin_unlock_irqrestore(&iommu->lock, flags);
|
|
}
|
|
|
|
const struct dma_ops sun4u_dma_ops = {
|
|
.alloc_coherent = dma_4u_alloc_coherent,
|
|
.free_coherent = dma_4u_free_coherent,
|
|
.map_single = dma_4u_map_single,
|
|
.unmap_single = dma_4u_unmap_single,
|
|
.map_sg = dma_4u_map_sg,
|
|
.unmap_sg = dma_4u_unmap_sg,
|
|
.sync_single_for_cpu = dma_4u_sync_single_for_cpu,
|
|
.sync_sg_for_cpu = dma_4u_sync_sg_for_cpu,
|
|
};
|
|
|
|
const struct dma_ops *dma_ops = &sun4u_dma_ops;
|
|
EXPORT_SYMBOL(dma_ops);
|
|
|
|
int dma_supported(struct device *dev, u64 device_mask)
|
|
{
|
|
struct iommu *iommu = dev->archdata.iommu;
|
|
u64 dma_addr_mask = iommu->dma_addr_mask;
|
|
|
|
if (device_mask >= (1UL << 32UL))
|
|
return 0;
|
|
|
|
if ((device_mask & dma_addr_mask) == dma_addr_mask)
|
|
return 1;
|
|
|
|
#ifdef CONFIG_PCI
|
|
if (dev->bus == &pci_bus_type)
|
|
return pci_dma_supported(to_pci_dev(dev), device_mask);
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL(dma_supported);
|
|
|
|
int dma_set_mask(struct device *dev, u64 dma_mask)
|
|
{
|
|
#ifdef CONFIG_PCI
|
|
if (dev->bus == &pci_bus_type)
|
|
return pci_set_dma_mask(to_pci_dev(dev), dma_mask);
|
|
#endif
|
|
return -EINVAL;
|
|
}
|
|
EXPORT_SYMBOL(dma_set_mask);
|