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e9b60476be
This test checks that the memory tag is present after mte allocation and the memory is accessible with those tags. This testcase verifies all sync, async and none mte error reporting mode. The allocated mte buffers are verified for Allocated range (no error expected while accessing buffer), Underflow range, and Overflow range. Different test scenarios covered here are, * Verify that mte memory are accessible at byte/block level. * Force underflow and overflow to occur and check the data consistency. * Check to/from between tagged and untagged memory. * Check that initial allocated memory to have 0 tag. This change also creates the necessary infrastructure to add mte test cases. MTE kselftests can use the several utility functions provided here to add wide variety of mte test scenarios. GCC compiler need flag '-march=armv8.5-a+memtag' so those flags are verified before compilation. The mte testcases can be launched with kselftest framework as, make TARGETS=arm64 ARM64_SUBTARGETS=mte kselftest or compiled as, make -C tools/testing/selftests TARGETS=arm64 ARM64_SUBTARGETS=mte CC='compiler' Co-developed-by: Gabor Kertesz <gabor.kertesz@arm.com> Signed-off-by: Gabor Kertesz <gabor.kertesz@arm.com> Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com> Tested-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Cc: Shuah Khan <shuah@kernel.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Link: https://lore.kernel.org/r/20201002115630.24683-2-amit.kachhap@arm.com Signed-off-by: Will Deacon <will@kernel.org>
60 lines
1.7 KiB
C
60 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (C) 2020 ARM Limited */
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/*
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* Below definitions may be found in kernel headers, However, they are
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* redefined here to decouple the MTE selftests compilations from them.
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*/
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#ifndef SEGV_MTEAERR
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#define SEGV_MTEAERR 8
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#endif
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#ifndef SEGV_MTESERR
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#define SEGV_MTESERR 9
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#endif
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#ifndef PROT_MTE
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#define PROT_MTE 0x20
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#endif
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#ifndef HWCAP2_MTE
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#define HWCAP2_MTE (1 << 18)
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#endif
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#ifndef PR_MTE_TCF_SHIFT
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#define PR_MTE_TCF_SHIFT 1
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#endif
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#ifndef PR_MTE_TCF_NONE
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#define PR_MTE_TCF_NONE (0UL << PR_MTE_TCF_SHIFT)
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#endif
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#ifndef PR_MTE_TCF_SYNC
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#define PR_MTE_TCF_SYNC (1UL << PR_MTE_TCF_SHIFT)
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#endif
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#ifndef PR_MTE_TCF_ASYNC
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#define PR_MTE_TCF_ASYNC (2UL << PR_MTE_TCF_SHIFT)
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#endif
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#ifndef PR_MTE_TAG_SHIFT
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#define PR_MTE_TAG_SHIFT 3
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#endif
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/* MTE Hardware feature definitions below. */
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#define MT_TAG_SHIFT 56
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#define MT_TAG_MASK 0xFUL
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#define MT_FREE_TAG 0x0UL
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#define MT_GRANULE_SIZE 16
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#define MT_TAG_COUNT 16
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#define MT_INCLUDE_TAG_MASK 0xFFFF
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#define MT_EXCLUDE_TAG_MASK 0x0
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#define MT_ALIGN_GRANULE (MT_GRANULE_SIZE - 1)
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#define MT_CLEAR_TAG(x) ((x) & ~(MT_TAG_MASK << MT_TAG_SHIFT))
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#define MT_SET_TAG(x, y) ((x) | (y << MT_TAG_SHIFT))
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#define MT_FETCH_TAG(x) ((x >> MT_TAG_SHIFT) & (MT_TAG_MASK))
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#define MT_ALIGN_UP(x) ((x + MT_ALIGN_GRANULE) & ~(MT_ALIGN_GRANULE))
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#define MT_PSTATE_TCO_SHIFT 25
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#define MT_PSTATE_TCO_MASK ~(0x1 << MT_PSTATE_TCO_SHIFT)
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#define MT_PSTATE_TCO_EN 1
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#define MT_PSTATE_TCO_DIS 0
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#define MT_EXCLUDE_TAG(x) (1 << (x))
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#define MT_INCLUDE_VALID_TAG(x) (MT_INCLUDE_TAG_MASK ^ MT_EXCLUDE_TAG(x))
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#define MT_INCLUDE_VALID_TAGS(x) (MT_INCLUDE_TAG_MASK ^ (x))
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#define MTE_ALLOW_NON_ZERO_TAG MT_INCLUDE_VALID_TAG(0)
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