Boris BREZILLON 1a748d2bc5 clk: at91: add PMC pll clocks ... This patch adds new at91 pll clock implementation using common clk framework. The pll clock layout describe the PLLX register layout. There are four pll clock layouts: - at91rm9200 - at91sam9g20 - at91sam9g45 - sama5d3 PLL clocks are given characteristics: - min/max clock source rate - ranges of valid clock output rates - values to set in out and icpll fields for each supported output range These characteristics are checked during rate change to avoid over/underclocking. These characteristics are described in atmel's SoC datasheet in "Electrical Characteristics" paragraph. Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>		2013-12-02 15:31:22 +01:00
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clk-main.c	clk: at91: add PMC main clock	2013-12-02 15:31:22 +01:00
clk-pll.c	clk: at91: add PMC pll clocks	2013-12-02 15:31:22 +01:00
clk-plldiv.c	clk: at91: add PMC pll clocks	2013-12-02 15:31:22 +01:00
Makefile	clk: at91: add PMC pll clocks	2013-12-02 15:31:22 +01:00
pmc.c	clk: at91: add PMC pll clocks	2013-12-02 15:31:22 +01:00
pmc.h	clk: at91: add PMC pll clocks	2013-12-02 15:31:22 +01:00