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f5fc0f86b0
This driver supports the wl1271 chipset from Texas Instruments based on the WiLink(tm) 6.0 mobile platform. Support for wl1273 should be relatively easy to add. This chipset is designed for embedded devices, with good powersaving capabilities. The wl1271 chipset is the successor of wl1251 and supports the 802.11b/g/n standards, but currently this driver supports only b/g. More information about this chipset can be found here: http://focus.ti.com/general/docs/wtbu/wtbuproductcontent.tsp?templateId=6123&navigationId=12762&contentId=29993 Signed-off-by: Luciano Coelho <luciano.coelho@nokia.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
72 lines
1.8 KiB
C
72 lines
1.8 KiB
C
/*
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* This file is part of wl1271
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*
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* Copyright (C) 2008-2009 Nokia Corporation
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*
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* Contact: Luciano Coelho <luciano.coelho@nokia.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
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* 02110-1301 USA
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*
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*/
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#ifndef __BOOT_H__
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#define __BOOT_H__
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#include "wl1271.h"
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int wl1271_boot(struct wl1271 *wl);
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#define WL1271_NO_SUBBANDS 8
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#define WL1271_NO_POWER_LEVELS 4
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#define WL1271_FW_VERSION_MAX_LEN 20
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struct wl1271_static_data {
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u8 mac_address[ETH_ALEN];
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u8 padding[2];
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u8 fw_version[WL1271_FW_VERSION_MAX_LEN];
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u32 hw_version;
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u8 tx_power_table[WL1271_NO_SUBBANDS][WL1271_NO_POWER_LEVELS];
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};
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/* number of times we try to read the INIT interrupt */
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#define INIT_LOOP 20000
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/* delay between retries */
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#define INIT_LOOP_DELAY 50
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#define REF_CLOCK 2
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#define WU_COUNTER_PAUSE_VAL 0x3FF
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#define WELP_ARM_COMMAND_VAL 0x4
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#define OCP_CMD_LOOP 32
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#define OCP_CMD_WRITE 0x1
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#define OCP_CMD_READ 0x2
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#define OCP_READY_MASK BIT(18)
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#define OCP_STATUS_MASK (BIT(16) | BIT(17))
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#define OCP_STATUS_NO_RESP 0x00000
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#define OCP_STATUS_OK 0x10000
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#define OCP_STATUS_REQ_FAILED 0x20000
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#define OCP_STATUS_RESP_ERROR 0x30000
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#define OCP_REG_POLARITY 0x30032
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#define CMD_MBOX_ADDRESS 0x407B4
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#define POLARITY_LOW BIT(1)
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#endif
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