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![Guennadi Liakhovetski](/assets/img/avatar_default.png)
On r-/sh-mobile SoCs MSTP clocks are used by the runtime PM to dynamically enable and disable peripheral clocks. To make sure the clock has really started we have to read back its status register until it confirms success. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
216 lines
6.1 KiB
C
216 lines
6.1 KiB
C
#ifndef __SH_CLOCK_H
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#define __SH_CLOCK_H
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#include <linux/list.h>
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#include <linux/seq_file.h>
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#include <linux/cpufreq.h>
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#include <linux/types.h>
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#include <linux/kref.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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struct clk;
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struct clk_mapping {
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phys_addr_t phys;
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void __iomem *base;
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unsigned long len;
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struct kref ref;
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};
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struct sh_clk_ops {
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#ifdef CONFIG_SH_CLK_CPG_LEGACY
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void (*init)(struct clk *clk);
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#endif
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int (*enable)(struct clk *clk);
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void (*disable)(struct clk *clk);
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unsigned long (*recalc)(struct clk *clk);
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int (*set_rate)(struct clk *clk, unsigned long rate);
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int (*set_parent)(struct clk *clk, struct clk *parent);
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long (*round_rate)(struct clk *clk, unsigned long rate);
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};
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#define SH_CLK_DIV_MSK(div) ((1 << (div)) - 1)
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#define SH_CLK_DIV4_MSK SH_CLK_DIV_MSK(4)
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#define SH_CLK_DIV6_MSK SH_CLK_DIV_MSK(6)
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struct clk {
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struct list_head node;
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struct clk *parent;
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struct clk **parent_table; /* list of parents to */
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unsigned short parent_num; /* choose between */
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unsigned char src_shift; /* source clock field in the */
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unsigned char src_width; /* configuration register */
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struct sh_clk_ops *ops;
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struct list_head children;
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struct list_head sibling; /* node for children */
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int usecount;
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unsigned long rate;
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unsigned long flags;
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void __iomem *enable_reg;
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void __iomem *status_reg;
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unsigned int enable_bit;
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void __iomem *mapped_reg;
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unsigned int div_mask;
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unsigned long arch_flags;
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void *priv;
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struct clk_mapping *mapping;
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struct cpufreq_frequency_table *freq_table;
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unsigned int nr_freqs;
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};
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#define CLK_ENABLE_ON_INIT BIT(0)
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#define CLK_ENABLE_REG_32BIT BIT(1) /* default access size */
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#define CLK_ENABLE_REG_16BIT BIT(2)
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#define CLK_ENABLE_REG_8BIT BIT(3)
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#define CLK_MASK_DIV_ON_DISABLE BIT(4)
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#define CLK_ENABLE_REG_MASK (CLK_ENABLE_REG_32BIT | \
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CLK_ENABLE_REG_16BIT | \
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CLK_ENABLE_REG_8BIT)
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/* drivers/sh/clk.c */
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unsigned long followparent_recalc(struct clk *);
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void recalculate_root_clocks(void);
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void propagate_rate(struct clk *);
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int clk_reparent(struct clk *child, struct clk *parent);
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int clk_register(struct clk *);
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void clk_unregister(struct clk *);
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void clk_enable_init_clocks(void);
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struct clk_div_mult_table {
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unsigned int *divisors;
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unsigned int nr_divisors;
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unsigned int *multipliers;
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unsigned int nr_multipliers;
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};
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struct cpufreq_frequency_table;
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void clk_rate_table_build(struct clk *clk,
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struct cpufreq_frequency_table *freq_table,
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int nr_freqs,
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struct clk_div_mult_table *src_table,
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unsigned long *bitmap);
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long clk_rate_table_round(struct clk *clk,
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struct cpufreq_frequency_table *freq_table,
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unsigned long rate);
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int clk_rate_table_find(struct clk *clk,
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struct cpufreq_frequency_table *freq_table,
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unsigned long rate);
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long clk_rate_div_range_round(struct clk *clk, unsigned int div_min,
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unsigned int div_max, unsigned long rate);
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long clk_rate_mult_range_round(struct clk *clk, unsigned int mult_min,
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unsigned int mult_max, unsigned long rate);
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long clk_round_parent(struct clk *clk, unsigned long target,
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unsigned long *best_freq, unsigned long *parent_freq,
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unsigned int div_min, unsigned int div_max);
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#define SH_CLK_MSTP(_parent, _enable_reg, _enable_bit, _status_reg, _flags) \
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{ \
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.parent = _parent, \
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.enable_reg = (void __iomem *)_enable_reg, \
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.enable_bit = _enable_bit, \
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.status_reg = _status_reg, \
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.flags = _flags, \
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}
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#define SH_CLK_MSTP32(_p, _r, _b, _f) \
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SH_CLK_MSTP(_p, _r, _b, 0, _f | CLK_ENABLE_REG_32BIT)
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#define SH_CLK_MSTP32_STS(_p, _r, _b, _s, _f) \
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SH_CLK_MSTP(_p, _r, _b, _s, _f | CLK_ENABLE_REG_32BIT)
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#define SH_CLK_MSTP16(_p, _r, _b, _f) \
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SH_CLK_MSTP(_p, _r, _b, 0, _f | CLK_ENABLE_REG_16BIT)
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#define SH_CLK_MSTP8(_p, _r, _b, _f) \
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SH_CLK_MSTP(_p, _r, _b, 0, _f | CLK_ENABLE_REG_8BIT)
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int sh_clk_mstp_register(struct clk *clks, int nr);
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/*
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* MSTP registration never really cared about access size, despite the
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* original enable/disable pairs assuming a 32-bit access. Clocks are
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* responsible for defining their access sizes either directly or via the
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* clock definition wrappers.
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*/
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static inline int __deprecated sh_clk_mstp32_register(struct clk *clks, int nr)
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{
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return sh_clk_mstp_register(clks, nr);
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}
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#define SH_CLK_DIV4(_parent, _reg, _shift, _div_bitmap, _flags) \
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{ \
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.parent = _parent, \
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.enable_reg = (void __iomem *)_reg, \
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.enable_bit = _shift, \
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.arch_flags = _div_bitmap, \
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.div_mask = SH_CLK_DIV4_MSK, \
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.flags = _flags, \
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}
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struct clk_div_table {
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struct clk_div_mult_table *div_mult_table;
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void (*kick)(struct clk *clk);
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};
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#define clk_div4_table clk_div_table
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int sh_clk_div4_register(struct clk *clks, int nr,
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struct clk_div4_table *table);
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int sh_clk_div4_enable_register(struct clk *clks, int nr,
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struct clk_div4_table *table);
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int sh_clk_div4_reparent_register(struct clk *clks, int nr,
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struct clk_div4_table *table);
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#define SH_CLK_DIV6_EXT(_reg, _flags, _parents, \
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_num_parents, _src_shift, _src_width) \
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{ \
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.enable_reg = (void __iomem *)_reg, \
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.enable_bit = 0, /* unused */ \
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.flags = _flags | CLK_MASK_DIV_ON_DISABLE, \
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.div_mask = SH_CLK_DIV6_MSK, \
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.parent_table = _parents, \
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.parent_num = _num_parents, \
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.src_shift = _src_shift, \
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.src_width = _src_width, \
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}
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#define SH_CLK_DIV6(_parent, _reg, _flags) \
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{ \
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.parent = _parent, \
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.enable_reg = (void __iomem *)_reg, \
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.enable_bit = 0, /* unused */ \
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.div_mask = SH_CLK_DIV6_MSK, \
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.flags = _flags | CLK_MASK_DIV_ON_DISABLE, \
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}
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int sh_clk_div6_register(struct clk *clks, int nr);
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int sh_clk_div6_reparent_register(struct clk *clks, int nr);
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#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
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#define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
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#define CLKDEV_ICK_ID(_cid, _did, _clk) { .con_id = _cid, .dev_id = _did, .clk = _clk }
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/* .enable_reg will be updated to .mapping on sh_clk_fsidiv_register() */
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#define SH_CLK_FSIDIV(_reg, _parent) \
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{ \
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.enable_reg = (void __iomem *)_reg, \
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.parent = _parent, \
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}
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int sh_clk_fsidiv_register(struct clk *clks, int nr);
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#endif /* __SH_CLOCK_H */
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