427 lines
12 KiB
C
427 lines
12 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_X86_TLBFLUSH_H
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#define _ASM_X86_TLBFLUSH_H
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#include <linux/mm_types.h>
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#include <linux/mmu_notifier.h>
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#include <linux/sched.h>
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#include <asm/processor.h>
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#include <asm/cpufeature.h>
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#include <asm/special_insns.h>
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#include <asm/smp.h>
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#include <asm/invpcid.h>
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#include <asm/pti.h>
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#include <asm/processor-flags.h>
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#include <asm/pgtable.h>
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DECLARE_PER_CPU(u64, tlbstate_untag_mask);
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void __flush_tlb_all(void);
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#define TLB_FLUSH_ALL -1UL
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#define TLB_GENERATION_INVALID 0
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void cr4_update_irqsoff(unsigned long set, unsigned long clear);
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unsigned long cr4_read_shadow(void);
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/* Set in this cpu's CR4. */
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static inline void cr4_set_bits_irqsoff(unsigned long mask)
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{
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cr4_update_irqsoff(mask, 0);
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}
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/* Clear in this cpu's CR4. */
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static inline void cr4_clear_bits_irqsoff(unsigned long mask)
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{
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cr4_update_irqsoff(0, mask);
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}
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/* Set in this cpu's CR4. */
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static inline void cr4_set_bits(unsigned long mask)
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{
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unsigned long flags;
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local_irq_save(flags);
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cr4_set_bits_irqsoff(mask);
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local_irq_restore(flags);
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}
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/* Clear in this cpu's CR4. */
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static inline void cr4_clear_bits(unsigned long mask)
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{
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unsigned long flags;
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local_irq_save(flags);
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cr4_clear_bits_irqsoff(mask);
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local_irq_restore(flags);
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}
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#ifndef MODULE
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/*
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* 6 because 6 should be plenty and struct tlb_state will fit in two cache
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* lines.
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*/
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#define TLB_NR_DYN_ASIDS 6
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struct tlb_context {
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u64 ctx_id;
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u64 tlb_gen;
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};
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struct tlb_state {
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/*
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* cpu_tlbstate.loaded_mm should match CR3 whenever interrupts
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* are on. This means that it may not match current->active_mm,
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* which will contain the previous user mm when we're in lazy TLB
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* mode even if we've already switched back to swapper_pg_dir.
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*
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* During switch_mm_irqs_off(), loaded_mm will be set to
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* LOADED_MM_SWITCHING during the brief interrupts-off window
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* when CR3 and loaded_mm would otherwise be inconsistent. This
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* is for nmi_uaccess_okay()'s benefit.
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*/
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struct mm_struct *loaded_mm;
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#define LOADED_MM_SWITCHING ((struct mm_struct *)1UL)
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/* Last user mm for optimizing IBPB */
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union {
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struct mm_struct *last_user_mm;
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unsigned long last_user_mm_spec;
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};
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u16 loaded_mm_asid;
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u16 next_asid;
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/*
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* If set we changed the page tables in such a way that we
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* needed an invalidation of all contexts (aka. PCIDs / ASIDs).
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* This tells us to go invalidate all the non-loaded ctxs[]
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* on the next context switch.
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*
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* The current ctx was kept up-to-date as it ran and does not
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* need to be invalidated.
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*/
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bool invalidate_other;
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#ifdef CONFIG_ADDRESS_MASKING
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/*
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* Active LAM mode.
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*
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* X86_CR3_LAM_U57/U48 shifted right by X86_CR3_LAM_U57_BIT or 0 if LAM
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* disabled.
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*/
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u8 lam;
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#endif
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/*
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* Mask that contains TLB_NR_DYN_ASIDS+1 bits to indicate
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* the corresponding user PCID needs a flush next time we
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* switch to it; see SWITCH_TO_USER_CR3.
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*/
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unsigned short user_pcid_flush_mask;
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/*
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* Access to this CR4 shadow and to H/W CR4 is protected by
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* disabling interrupts when modifying either one.
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*/
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unsigned long cr4;
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/*
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* This is a list of all contexts that might exist in the TLB.
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* There is one per ASID that we use, and the ASID (what the
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* CPU calls PCID) is the index into ctxts.
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*
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* For each context, ctx_id indicates which mm the TLB's user
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* entries came from. As an invariant, the TLB will never
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* contain entries that are out-of-date as when that mm reached
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* the tlb_gen in the list.
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*
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* To be clear, this means that it's legal for the TLB code to
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* flush the TLB without updating tlb_gen. This can happen
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* (for now, at least) due to paravirt remote flushes.
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*
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* NB: context 0 is a bit special, since it's also used by
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* various bits of init code. This is fine -- code that
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* isn't aware of PCID will end up harmlessly flushing
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* context 0.
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*/
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struct tlb_context ctxs[TLB_NR_DYN_ASIDS];
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};
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DECLARE_PER_CPU_ALIGNED(struct tlb_state, cpu_tlbstate);
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struct tlb_state_shared {
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/*
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* We can be in one of several states:
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*
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* - Actively using an mm. Our CPU's bit will be set in
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* mm_cpumask(loaded_mm) and is_lazy == false;
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*
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* - Not using a real mm. loaded_mm == &init_mm. Our CPU's bit
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* will not be set in mm_cpumask(&init_mm) and is_lazy == false.
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*
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* - Lazily using a real mm. loaded_mm != &init_mm, our bit
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* is set in mm_cpumask(loaded_mm), but is_lazy == true.
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* We're heuristically guessing that the CR3 load we
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* skipped more than makes up for the overhead added by
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* lazy mode.
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*/
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bool is_lazy;
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};
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DECLARE_PER_CPU_SHARED_ALIGNED(struct tlb_state_shared, cpu_tlbstate_shared);
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bool nmi_uaccess_okay(void);
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#define nmi_uaccess_okay nmi_uaccess_okay
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/* Initialize cr4 shadow for this CPU. */
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static inline void cr4_init_shadow(void)
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{
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this_cpu_write(cpu_tlbstate.cr4, __read_cr4());
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}
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extern unsigned long mmu_cr4_features;
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extern u32 *trampoline_cr4_features;
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extern void initialize_tlbstate_and_flush(void);
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/*
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* TLB flushing:
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*
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* - flush_tlb_all() flushes all processes TLBs
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* - flush_tlb_mm(mm) flushes the specified mm context TLB's
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* - flush_tlb_page(vma, vmaddr) flushes one page
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* - flush_tlb_range(vma, start, end) flushes a range of pages
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* - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
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* - flush_tlb_multi(cpumask, info) flushes TLBs on multiple cpus
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*
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* ..but the i386 has somewhat limited tlb flushing capabilities,
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* and page-granular flushes are available only on i486 and up.
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*/
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struct flush_tlb_info {
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/*
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* We support several kinds of flushes.
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*
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* - Fully flush a single mm. .mm will be set, .end will be
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* TLB_FLUSH_ALL, and .new_tlb_gen will be the tlb_gen to
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* which the IPI sender is trying to catch us up.
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*
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* - Partially flush a single mm. .mm will be set, .start and
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* .end will indicate the range, and .new_tlb_gen will be set
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* such that the changes between generation .new_tlb_gen-1 and
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* .new_tlb_gen are entirely contained in the indicated range.
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*
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* - Fully flush all mms whose tlb_gens have been updated. .mm
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* will be NULL, .end will be TLB_FLUSH_ALL, and .new_tlb_gen
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* will be zero.
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*/
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struct mm_struct *mm;
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unsigned long start;
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unsigned long end;
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u64 new_tlb_gen;
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unsigned int initiating_cpu;
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u8 stride_shift;
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u8 freed_tables;
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};
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void flush_tlb_local(void);
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void flush_tlb_one_user(unsigned long addr);
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void flush_tlb_one_kernel(unsigned long addr);
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void flush_tlb_multi(const struct cpumask *cpumask,
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const struct flush_tlb_info *info);
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#ifdef CONFIG_PARAVIRT
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#include <asm/paravirt.h>
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#endif
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#define flush_tlb_mm(mm) \
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flush_tlb_mm_range(mm, 0UL, TLB_FLUSH_ALL, 0UL, true)
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#define flush_tlb_range(vma, start, end) \
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flush_tlb_mm_range((vma)->vm_mm, start, end, \
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((vma)->vm_flags & VM_HUGETLB) \
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? huge_page_shift(hstate_vma(vma)) \
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: PAGE_SHIFT, false)
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extern void flush_tlb_all(void);
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extern void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start,
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unsigned long end, unsigned int stride_shift,
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bool freed_tables);
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extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
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static inline void flush_tlb_page(struct vm_area_struct *vma, unsigned long a)
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{
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flush_tlb_mm_range(vma->vm_mm, a, a + PAGE_SIZE, PAGE_SHIFT, false);
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}
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static inline bool arch_tlbbatch_should_defer(struct mm_struct *mm)
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{
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bool should_defer = false;
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/* If remote CPUs need to be flushed then defer batch the flush */
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if (cpumask_any_but(mm_cpumask(mm), get_cpu()) < nr_cpu_ids)
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should_defer = true;
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put_cpu();
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return should_defer;
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}
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static inline u64 inc_mm_tlb_gen(struct mm_struct *mm)
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{
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/*
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* Bump the generation count. This also serves as a full barrier
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* that synchronizes with switch_mm(): callers are required to order
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* their read of mm_cpumask after their writes to the paging
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* structures.
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*/
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return atomic64_inc_return(&mm->context.tlb_gen);
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}
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static inline void arch_tlbbatch_add_pending(struct arch_tlbflush_unmap_batch *batch,
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struct mm_struct *mm,
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unsigned long uaddr)
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{
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inc_mm_tlb_gen(mm);
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cpumask_or(&batch->cpumask, &batch->cpumask, mm_cpumask(mm));
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mmu_notifier_arch_invalidate_secondary_tlbs(mm, 0, -1UL);
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}
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static inline void arch_flush_tlb_batched_pending(struct mm_struct *mm)
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{
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flush_tlb_mm(mm);
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}
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extern void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch);
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static inline bool pte_flags_need_flush(unsigned long oldflags,
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unsigned long newflags,
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bool ignore_access)
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{
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/*
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* Flags that require a flush when cleared but not when they are set.
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* Only include flags that would not trigger spurious page-faults.
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* Non-present entries are not cached. Hardware would set the
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* dirty/access bit if needed without a fault.
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*/
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const pteval_t flush_on_clear = _PAGE_DIRTY | _PAGE_PRESENT |
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_PAGE_ACCESSED;
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const pteval_t software_flags = _PAGE_SOFTW1 | _PAGE_SOFTW2 |
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_PAGE_SOFTW3 | _PAGE_SOFTW4;
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const pteval_t flush_on_change = _PAGE_RW | _PAGE_USER | _PAGE_PWT |
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_PAGE_PCD | _PAGE_PSE | _PAGE_GLOBAL | _PAGE_PAT |
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_PAGE_PAT_LARGE | _PAGE_PKEY_BIT0 | _PAGE_PKEY_BIT1 |
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_PAGE_PKEY_BIT2 | _PAGE_PKEY_BIT3 | _PAGE_NX;
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unsigned long diff = oldflags ^ newflags;
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BUILD_BUG_ON(flush_on_clear & software_flags);
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BUILD_BUG_ON(flush_on_clear & flush_on_change);
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BUILD_BUG_ON(flush_on_change & software_flags);
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/* Ignore software flags */
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diff &= ~software_flags;
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if (ignore_access)
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diff &= ~_PAGE_ACCESSED;
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/*
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* Did any of the 'flush_on_clear' flags was clleared set from between
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* 'oldflags' and 'newflags'?
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*/
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if (diff & oldflags & flush_on_clear)
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return true;
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/* Flush on modified flags. */
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if (diff & flush_on_change)
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return true;
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/* Ensure there are no flags that were left behind */
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if (IS_ENABLED(CONFIG_DEBUG_VM) &&
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(diff & ~(flush_on_clear | software_flags | flush_on_change))) {
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VM_WARN_ON_ONCE(1);
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return true;
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}
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return false;
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}
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/*
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* pte_needs_flush() checks whether permissions were demoted and require a
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* flush. It should only be used for userspace PTEs.
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*/
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static inline bool pte_needs_flush(pte_t oldpte, pte_t newpte)
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{
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/* !PRESENT -> * ; no need for flush */
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if (!(pte_flags(oldpte) & _PAGE_PRESENT))
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return false;
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/* PFN changed ; needs flush */
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if (pte_pfn(oldpte) != pte_pfn(newpte))
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return true;
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/*
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* check PTE flags; ignore access-bit; see comment in
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* ptep_clear_flush_young().
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*/
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return pte_flags_need_flush(pte_flags(oldpte), pte_flags(newpte),
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true);
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}
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#define pte_needs_flush pte_needs_flush
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/*
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* huge_pmd_needs_flush() checks whether permissions were demoted and require a
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* flush. It should only be used for userspace huge PMDs.
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*/
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static inline bool huge_pmd_needs_flush(pmd_t oldpmd, pmd_t newpmd)
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{
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/* !PRESENT -> * ; no need for flush */
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if (!(pmd_flags(oldpmd) & _PAGE_PRESENT))
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return false;
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/* PFN changed ; needs flush */
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if (pmd_pfn(oldpmd) != pmd_pfn(newpmd))
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return true;
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/*
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* check PMD flags; do not ignore access-bit; see
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* pmdp_clear_flush_young().
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*/
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return pte_flags_need_flush(pmd_flags(oldpmd), pmd_flags(newpmd),
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false);
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}
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#define huge_pmd_needs_flush huge_pmd_needs_flush
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#ifdef CONFIG_ADDRESS_MASKING
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static inline u64 tlbstate_lam_cr3_mask(void)
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{
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u64 lam = this_cpu_read(cpu_tlbstate.lam);
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return lam << X86_CR3_LAM_U57_BIT;
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}
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static inline void set_tlbstate_lam_mode(struct mm_struct *mm)
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{
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this_cpu_write(cpu_tlbstate.lam,
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mm->context.lam_cr3_mask >> X86_CR3_LAM_U57_BIT);
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this_cpu_write(tlbstate_untag_mask, mm->context.untag_mask);
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}
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#else
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static inline u64 tlbstate_lam_cr3_mask(void)
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{
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return 0;
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}
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static inline void set_tlbstate_lam_mode(struct mm_struct *mm)
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{
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}
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#endif
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#endif /* !MODULE */
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static inline void __native_tlb_flush_global(unsigned long cr4)
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{
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native_write_cr4(cr4 ^ X86_CR4_PGE);
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native_write_cr4(cr4);
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}
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#endif /* _ASM_X86_TLBFLUSH_H */
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