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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-24 09:50:04 +00:00
![Rob Herring](/assets/img/avatar_default.png)
The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20230714174628.4057920-1-robh@kernel.org Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
417 lines
10 KiB
C
417 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2014-2015 Imagination Technologies Ltd.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/regulator/consumer.h>
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#include <linux/slab.h>
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#include <linux/iio/buffer.h>
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#include <linux/iio/iio.h>
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#include <linux/iio/sysfs.h>
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#include <linux/iio/trigger.h>
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#include <linux/iio/trigger_consumer.h>
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#include <linux/iio/triggered_buffer.h>
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/* Registers */
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#define CC10001_ADC_CONFIG 0x00
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#define CC10001_ADC_START_CONV BIT(4)
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#define CC10001_ADC_MODE_SINGLE_CONV BIT(5)
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#define CC10001_ADC_DDATA_OUT 0x04
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#define CC10001_ADC_EOC 0x08
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#define CC10001_ADC_EOC_SET BIT(0)
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#define CC10001_ADC_CHSEL_SAMPLED 0x0c
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#define CC10001_ADC_POWER_DOWN 0x10
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#define CC10001_ADC_POWER_DOWN_SET BIT(0)
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#define CC10001_ADC_DEBUG 0x14
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#define CC10001_ADC_DATA_COUNT 0x20
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#define CC10001_ADC_DATA_MASK GENMASK(9, 0)
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#define CC10001_ADC_NUM_CHANNELS 8
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#define CC10001_ADC_CH_MASK GENMASK(2, 0)
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#define CC10001_INVALID_SAMPLED 0xffff
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#define CC10001_MAX_POLL_COUNT 20
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/*
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* As per device specification, wait six clock cycles after power-up to
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* activate START. Since adding two more clock cycles delay does not
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* impact the performance too much, we are adding two additional cycles delay
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* intentionally here.
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*/
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#define CC10001_WAIT_CYCLES 8
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struct cc10001_adc_device {
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void __iomem *reg_base;
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struct clk *adc_clk;
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struct regulator *reg;
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u16 *buf;
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bool shared;
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struct mutex lock;
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unsigned int start_delay_ns;
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unsigned int eoc_delay_ns;
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};
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static inline void cc10001_adc_write_reg(struct cc10001_adc_device *adc_dev,
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u32 reg, u32 val)
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{
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writel(val, adc_dev->reg_base + reg);
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}
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static inline u32 cc10001_adc_read_reg(struct cc10001_adc_device *adc_dev,
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u32 reg)
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{
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return readl(adc_dev->reg_base + reg);
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}
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static void cc10001_adc_power_up(struct cc10001_adc_device *adc_dev)
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{
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cc10001_adc_write_reg(adc_dev, CC10001_ADC_POWER_DOWN, 0);
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ndelay(adc_dev->start_delay_ns);
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}
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static void cc10001_adc_power_down(struct cc10001_adc_device *adc_dev)
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{
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cc10001_adc_write_reg(adc_dev, CC10001_ADC_POWER_DOWN,
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CC10001_ADC_POWER_DOWN_SET);
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}
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static void cc10001_adc_start(struct cc10001_adc_device *adc_dev,
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unsigned int channel)
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{
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u32 val;
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/* Channel selection and mode of operation */
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val = (channel & CC10001_ADC_CH_MASK) | CC10001_ADC_MODE_SINGLE_CONV;
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cc10001_adc_write_reg(adc_dev, CC10001_ADC_CONFIG, val);
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udelay(1);
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val = cc10001_adc_read_reg(adc_dev, CC10001_ADC_CONFIG);
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val = val | CC10001_ADC_START_CONV;
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cc10001_adc_write_reg(adc_dev, CC10001_ADC_CONFIG, val);
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}
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static u16 cc10001_adc_poll_done(struct iio_dev *indio_dev,
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unsigned int channel,
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unsigned int delay)
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{
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struct cc10001_adc_device *adc_dev = iio_priv(indio_dev);
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unsigned int poll_count = 0;
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while (!(cc10001_adc_read_reg(adc_dev, CC10001_ADC_EOC) &
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CC10001_ADC_EOC_SET)) {
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ndelay(delay);
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if (poll_count++ == CC10001_MAX_POLL_COUNT)
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return CC10001_INVALID_SAMPLED;
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}
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poll_count = 0;
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while ((cc10001_adc_read_reg(adc_dev, CC10001_ADC_CHSEL_SAMPLED) &
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CC10001_ADC_CH_MASK) != channel) {
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ndelay(delay);
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if (poll_count++ == CC10001_MAX_POLL_COUNT)
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return CC10001_INVALID_SAMPLED;
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}
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/* Read the 10 bit output register */
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return cc10001_adc_read_reg(adc_dev, CC10001_ADC_DDATA_OUT) &
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CC10001_ADC_DATA_MASK;
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}
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static irqreturn_t cc10001_adc_trigger_h(int irq, void *p)
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{
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struct cc10001_adc_device *adc_dev;
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struct iio_poll_func *pf = p;
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struct iio_dev *indio_dev;
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unsigned int delay_ns;
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unsigned int channel;
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unsigned int scan_idx;
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bool sample_invalid;
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u16 *data;
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int i;
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indio_dev = pf->indio_dev;
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adc_dev = iio_priv(indio_dev);
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data = adc_dev->buf;
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mutex_lock(&adc_dev->lock);
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if (!adc_dev->shared)
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cc10001_adc_power_up(adc_dev);
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/* Calculate delay step for eoc and sampled data */
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delay_ns = adc_dev->eoc_delay_ns / CC10001_MAX_POLL_COUNT;
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i = 0;
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sample_invalid = false;
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for_each_set_bit(scan_idx, indio_dev->active_scan_mask,
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indio_dev->masklength) {
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channel = indio_dev->channels[scan_idx].channel;
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cc10001_adc_start(adc_dev, channel);
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data[i] = cc10001_adc_poll_done(indio_dev, channel, delay_ns);
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if (data[i] == CC10001_INVALID_SAMPLED) {
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dev_warn(&indio_dev->dev,
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"invalid sample on channel %d\n", channel);
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sample_invalid = true;
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goto done;
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}
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i++;
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}
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done:
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if (!adc_dev->shared)
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cc10001_adc_power_down(adc_dev);
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mutex_unlock(&adc_dev->lock);
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if (!sample_invalid)
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iio_push_to_buffers_with_timestamp(indio_dev, data,
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iio_get_time_ns(indio_dev));
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iio_trigger_notify_done(indio_dev->trig);
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return IRQ_HANDLED;
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}
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static u16 cc10001_adc_read_raw_voltage(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan)
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{
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struct cc10001_adc_device *adc_dev = iio_priv(indio_dev);
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unsigned int delay_ns;
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u16 val;
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if (!adc_dev->shared)
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cc10001_adc_power_up(adc_dev);
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/* Calculate delay step for eoc and sampled data */
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delay_ns = adc_dev->eoc_delay_ns / CC10001_MAX_POLL_COUNT;
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cc10001_adc_start(adc_dev, chan->channel);
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val = cc10001_adc_poll_done(indio_dev, chan->channel, delay_ns);
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if (!adc_dev->shared)
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cc10001_adc_power_down(adc_dev);
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return val;
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}
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static int cc10001_adc_read_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int *val, int *val2, long mask)
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{
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struct cc10001_adc_device *adc_dev = iio_priv(indio_dev);
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int ret;
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switch (mask) {
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case IIO_CHAN_INFO_RAW:
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if (iio_buffer_enabled(indio_dev))
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return -EBUSY;
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mutex_lock(&adc_dev->lock);
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*val = cc10001_adc_read_raw_voltage(indio_dev, chan);
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mutex_unlock(&adc_dev->lock);
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if (*val == CC10001_INVALID_SAMPLED)
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return -EIO;
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return IIO_VAL_INT;
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case IIO_CHAN_INFO_SCALE:
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ret = regulator_get_voltage(adc_dev->reg);
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if (ret < 0)
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return ret;
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*val = ret / 1000;
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*val2 = chan->scan_type.realbits;
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return IIO_VAL_FRACTIONAL_LOG2;
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default:
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return -EINVAL;
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}
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}
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static int cc10001_update_scan_mode(struct iio_dev *indio_dev,
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const unsigned long *scan_mask)
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{
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struct cc10001_adc_device *adc_dev = iio_priv(indio_dev);
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kfree(adc_dev->buf);
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adc_dev->buf = kmalloc(indio_dev->scan_bytes, GFP_KERNEL);
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if (!adc_dev->buf)
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return -ENOMEM;
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return 0;
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}
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static const struct iio_info cc10001_adc_info = {
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.read_raw = &cc10001_adc_read_raw,
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.update_scan_mode = &cc10001_update_scan_mode,
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};
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static int cc10001_adc_channel_init(struct iio_dev *indio_dev,
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unsigned long channel_map)
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{
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struct iio_chan_spec *chan_array, *timestamp;
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unsigned int bit, idx = 0;
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indio_dev->num_channels = bitmap_weight(&channel_map,
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CC10001_ADC_NUM_CHANNELS) + 1;
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chan_array = devm_kcalloc(&indio_dev->dev, indio_dev->num_channels,
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sizeof(struct iio_chan_spec),
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GFP_KERNEL);
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if (!chan_array)
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return -ENOMEM;
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for_each_set_bit(bit, &channel_map, CC10001_ADC_NUM_CHANNELS) {
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struct iio_chan_spec *chan = &chan_array[idx];
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chan->type = IIO_VOLTAGE;
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chan->indexed = 1;
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chan->channel = bit;
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chan->scan_index = idx;
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chan->scan_type.sign = 'u';
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chan->scan_type.realbits = 10;
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chan->scan_type.storagebits = 16;
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chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE);
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chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
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idx++;
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}
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timestamp = &chan_array[idx];
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timestamp->type = IIO_TIMESTAMP;
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timestamp->channel = -1;
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timestamp->scan_index = idx;
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timestamp->scan_type.sign = 's';
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timestamp->scan_type.realbits = 64;
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timestamp->scan_type.storagebits = 64;
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indio_dev->channels = chan_array;
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return 0;
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}
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static void cc10001_reg_disable(void *priv)
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{
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regulator_disable(priv);
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}
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static void cc10001_pd_cb(void *priv)
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{
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cc10001_adc_power_down(priv);
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}
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static int cc10001_adc_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device_node *node = dev->of_node;
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struct cc10001_adc_device *adc_dev;
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unsigned long adc_clk_rate;
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struct iio_dev *indio_dev;
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unsigned long channel_map;
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int ret;
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indio_dev = devm_iio_device_alloc(dev, sizeof(*adc_dev));
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if (indio_dev == NULL)
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return -ENOMEM;
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adc_dev = iio_priv(indio_dev);
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channel_map = GENMASK(CC10001_ADC_NUM_CHANNELS - 1, 0);
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if (!of_property_read_u32(node, "adc-reserved-channels", &ret)) {
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adc_dev->shared = true;
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channel_map &= ~ret;
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}
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adc_dev->reg = devm_regulator_get(dev, "vref");
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if (IS_ERR(adc_dev->reg))
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return PTR_ERR(adc_dev->reg);
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ret = regulator_enable(adc_dev->reg);
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if (ret)
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return ret;
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ret = devm_add_action_or_reset(dev, cc10001_reg_disable, adc_dev->reg);
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if (ret)
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return ret;
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indio_dev->name = dev_name(dev);
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indio_dev->info = &cc10001_adc_info;
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indio_dev->modes = INDIO_DIRECT_MODE;
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adc_dev->reg_base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(adc_dev->reg_base))
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return PTR_ERR(adc_dev->reg_base);
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adc_dev->adc_clk = devm_clk_get_enabled(dev, "adc");
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if (IS_ERR(adc_dev->adc_clk)) {
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dev_err(dev, "failed to get/enable the clock\n");
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return PTR_ERR(adc_dev->adc_clk);
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}
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adc_clk_rate = clk_get_rate(adc_dev->adc_clk);
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if (!adc_clk_rate) {
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dev_err(dev, "null clock rate!\n");
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return -EINVAL;
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}
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adc_dev->eoc_delay_ns = NSEC_PER_SEC / adc_clk_rate;
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adc_dev->start_delay_ns = adc_dev->eoc_delay_ns * CC10001_WAIT_CYCLES;
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/*
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* There is only one register to power-up/power-down the AUX ADC.
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* If the ADC is shared among multiple CPUs, always power it up here.
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* If the ADC is used only by the MIPS, power-up/power-down at runtime.
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*/
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if (adc_dev->shared)
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cc10001_adc_power_up(adc_dev);
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ret = devm_add_action_or_reset(dev, cc10001_pd_cb, adc_dev);
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if (ret)
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return ret;
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/* Setup the ADC channels available on the device */
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ret = cc10001_adc_channel_init(indio_dev, channel_map);
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if (ret < 0)
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return ret;
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mutex_init(&adc_dev->lock);
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ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL,
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&cc10001_adc_trigger_h, NULL);
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if (ret < 0)
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return ret;
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return devm_iio_device_register(dev, indio_dev);
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}
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static const struct of_device_id cc10001_adc_dt_ids[] = {
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{ .compatible = "cosmic,10001-adc", },
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{ }
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};
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MODULE_DEVICE_TABLE(of, cc10001_adc_dt_ids);
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static struct platform_driver cc10001_adc_driver = {
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.driver = {
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.name = "cc10001-adc",
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.of_match_table = cc10001_adc_dt_ids,
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},
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.probe = cc10001_adc_probe,
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};
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module_platform_driver(cc10001_adc_driver);
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MODULE_AUTHOR("Phani Movva <Phani.Movva@imgtec.com>");
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MODULE_DESCRIPTION("Cosmic Circuits ADC driver");
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MODULE_LICENSE("GPL v2");
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