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![Uwe Kleine-König](/assets/img/avatar_default.png)
The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is ignored (apart from emitting a warning) and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new() which already returns void. Eventually after all drivers are converted, .remove_new() will be renamed to .remove(). Trivially convert this driver from always returning zero in the remove callback to the void returning variant. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/20230919174931.1417681-11-u.kleine-koenig@pengutronix.de Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
420 lines
10 KiB
C
420 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2014-2015 Pengutronix, Markus Pargmann <mpa@pengutronix.de>
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*
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* This is the driver for the imx25 GCQ (Generic Conversion Queue)
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* connected to the imx25 ADC.
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*/
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#include <dt-bindings/iio/adc/fsl-imx25-gcq.h>
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#include <linux/clk.h>
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#include <linux/iio/iio.h>
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#include <linux/interrupt.h>
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#include <linux/mfd/imx25-tsadc.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/regulator/consumer.h>
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#define MX25_GCQ_TIMEOUT (msecs_to_jiffies(2000))
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static const char * const driver_name = "mx25-gcq";
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enum mx25_gcq_cfgs {
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MX25_CFG_XP = 0,
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MX25_CFG_YP,
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MX25_CFG_XN,
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MX25_CFG_YN,
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MX25_CFG_WIPER,
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MX25_CFG_INAUX0,
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MX25_CFG_INAUX1,
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MX25_CFG_INAUX2,
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MX25_NUM_CFGS,
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};
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struct mx25_gcq_priv {
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struct regmap *regs;
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struct completion completed;
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struct clk *clk;
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int irq;
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struct regulator *vref[4];
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u32 channel_vref_mv[MX25_NUM_CFGS];
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/*
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* Lock to protect the device state during a potential concurrent
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* read access from userspace. Reading a raw value requires a sequence
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* of register writes, then a wait for a completion callback,
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* and finally a register read, during which userspace could issue
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* another read request. This lock protects a read access from
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* ocurring before another one has finished.
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*/
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struct mutex lock;
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};
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#define MX25_CQG_CHAN(chan, id) {\
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.type = IIO_VOLTAGE,\
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.indexed = 1,\
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.channel = chan,\
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
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BIT(IIO_CHAN_INFO_SCALE),\
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.datasheet_name = id,\
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}
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static const struct iio_chan_spec mx25_gcq_channels[MX25_NUM_CFGS] = {
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MX25_CQG_CHAN(MX25_CFG_XP, "xp"),
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MX25_CQG_CHAN(MX25_CFG_YP, "yp"),
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MX25_CQG_CHAN(MX25_CFG_XN, "xn"),
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MX25_CQG_CHAN(MX25_CFG_YN, "yn"),
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MX25_CQG_CHAN(MX25_CFG_WIPER, "wiper"),
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MX25_CQG_CHAN(MX25_CFG_INAUX0, "inaux0"),
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MX25_CQG_CHAN(MX25_CFG_INAUX1, "inaux1"),
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MX25_CQG_CHAN(MX25_CFG_INAUX2, "inaux2"),
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};
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static const char * const mx25_gcq_refp_names[] = {
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[MX25_ADC_REFP_YP] = "yp",
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[MX25_ADC_REFP_XP] = "xp",
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[MX25_ADC_REFP_INT] = "int",
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[MX25_ADC_REFP_EXT] = "ext",
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};
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static irqreturn_t mx25_gcq_irq(int irq, void *data)
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{
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struct mx25_gcq_priv *priv = data;
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u32 stats;
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regmap_read(priv->regs, MX25_ADCQ_SR, &stats);
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if (stats & MX25_ADCQ_SR_EOQ) {
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regmap_update_bits(priv->regs, MX25_ADCQ_MR,
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MX25_ADCQ_MR_EOQ_IRQ, MX25_ADCQ_MR_EOQ_IRQ);
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complete(&priv->completed);
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}
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/* Disable conversion queue run */
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regmap_update_bits(priv->regs, MX25_ADCQ_CR, MX25_ADCQ_CR_FQS, 0);
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/* Acknowledge all possible irqs */
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regmap_write(priv->regs, MX25_ADCQ_SR, MX25_ADCQ_SR_FRR |
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MX25_ADCQ_SR_FUR | MX25_ADCQ_SR_FOR |
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MX25_ADCQ_SR_EOQ | MX25_ADCQ_SR_PD);
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return IRQ_HANDLED;
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}
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static int mx25_gcq_get_raw_value(struct device *dev,
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struct iio_chan_spec const *chan,
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struct mx25_gcq_priv *priv,
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int *val)
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{
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long timeout;
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u32 data;
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/* Setup the configuration we want to use */
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regmap_write(priv->regs, MX25_ADCQ_ITEM_7_0,
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MX25_ADCQ_ITEM(0, chan->channel));
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regmap_update_bits(priv->regs, MX25_ADCQ_MR, MX25_ADCQ_MR_EOQ_IRQ, 0);
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/* Trigger queue for one run */
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regmap_update_bits(priv->regs, MX25_ADCQ_CR, MX25_ADCQ_CR_FQS,
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MX25_ADCQ_CR_FQS);
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timeout = wait_for_completion_interruptible_timeout(
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&priv->completed, MX25_GCQ_TIMEOUT);
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if (timeout < 0) {
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dev_err(dev, "ADC wait for measurement failed\n");
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return timeout;
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} else if (timeout == 0) {
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dev_err(dev, "ADC timed out\n");
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return -ETIMEDOUT;
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}
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regmap_read(priv->regs, MX25_ADCQ_FIFO, &data);
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*val = MX25_ADCQ_FIFO_DATA(data);
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return IIO_VAL_INT;
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}
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static int mx25_gcq_read_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan, int *val,
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int *val2, long mask)
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{
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struct mx25_gcq_priv *priv = iio_priv(indio_dev);
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int ret;
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switch (mask) {
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case IIO_CHAN_INFO_RAW:
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mutex_lock(&priv->lock);
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ret = mx25_gcq_get_raw_value(&indio_dev->dev, chan, priv, val);
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mutex_unlock(&priv->lock);
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return ret;
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case IIO_CHAN_INFO_SCALE:
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*val = priv->channel_vref_mv[chan->channel];
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*val2 = 12;
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return IIO_VAL_FRACTIONAL_LOG2;
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default:
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return -EINVAL;
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}
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}
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static const struct iio_info mx25_gcq_iio_info = {
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.read_raw = mx25_gcq_read_raw,
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};
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static const struct regmap_config mx25_gcq_regconfig = {
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.max_register = 0x5c,
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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};
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static int mx25_gcq_ext_regulator_setup(struct device *dev,
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struct mx25_gcq_priv *priv, u32 refp)
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{
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char reg_name[12];
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int ret;
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if (priv->vref[refp])
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return 0;
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ret = snprintf(reg_name, sizeof(reg_name), "vref-%s",
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mx25_gcq_refp_names[refp]);
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if (ret < 0)
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return ret;
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priv->vref[refp] = devm_regulator_get_optional(dev, reg_name);
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if (IS_ERR(priv->vref[refp]))
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return dev_err_probe(dev, PTR_ERR(priv->vref[refp]),
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"Error, trying to use external voltage reference without a %s regulator.",
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reg_name);
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return 0;
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}
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static int mx25_gcq_setup_cfgs(struct platform_device *pdev,
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struct mx25_gcq_priv *priv)
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{
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struct device_node *np = pdev->dev.of_node;
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struct device_node *child;
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struct device *dev = &pdev->dev;
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int ret, i;
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/*
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* Setup all configurations registers with a default conversion
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* configuration for each input
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*/
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for (i = 0; i < MX25_NUM_CFGS; ++i)
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regmap_write(priv->regs, MX25_ADCQ_CFG(i),
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MX25_ADCQ_CFG_YPLL_OFF |
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MX25_ADCQ_CFG_XNUR_OFF |
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MX25_ADCQ_CFG_XPUL_OFF |
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MX25_ADCQ_CFG_REFP_INT |
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MX25_ADCQ_CFG_IN(i) |
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MX25_ADCQ_CFG_REFN_NGND2);
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for_each_child_of_node(np, child) {
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u32 reg;
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u32 refp = MX25_ADCQ_CFG_REFP_INT;
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u32 refn = MX25_ADCQ_CFG_REFN_NGND2;
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ret = of_property_read_u32(child, "reg", ®);
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if (ret) {
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dev_err(dev, "Failed to get reg property\n");
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of_node_put(child);
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return ret;
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}
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if (reg >= MX25_NUM_CFGS) {
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dev_err(dev,
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"reg value is greater than the number of available configuration registers\n");
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of_node_put(child);
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return -EINVAL;
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}
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of_property_read_u32(child, "fsl,adc-refp", &refp);
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of_property_read_u32(child, "fsl,adc-refn", &refn);
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switch (refp) {
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case MX25_ADC_REFP_EXT:
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case MX25_ADC_REFP_XP:
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case MX25_ADC_REFP_YP:
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ret = mx25_gcq_ext_regulator_setup(&pdev->dev, priv, refp);
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if (ret) {
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of_node_put(child);
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return ret;
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}
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priv->channel_vref_mv[reg] =
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regulator_get_voltage(priv->vref[refp]);
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/* Conversion from uV to mV */
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priv->channel_vref_mv[reg] /= 1000;
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break;
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case MX25_ADC_REFP_INT:
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priv->channel_vref_mv[reg] = 2500;
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break;
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default:
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dev_err(dev, "Invalid positive reference %d\n", refp);
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of_node_put(child);
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return -EINVAL;
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}
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/*
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* Shift the read values to the correct positions within the
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* register.
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*/
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refp = MX25_ADCQ_CFG_REFP(refp);
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refn = MX25_ADCQ_CFG_REFN(refn);
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if ((refp & MX25_ADCQ_CFG_REFP_MASK) != refp) {
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dev_err(dev, "Invalid fsl,adc-refp property value\n");
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of_node_put(child);
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return -EINVAL;
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}
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if ((refn & MX25_ADCQ_CFG_REFN_MASK) != refn) {
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dev_err(dev, "Invalid fsl,adc-refn property value\n");
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of_node_put(child);
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return -EINVAL;
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}
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regmap_update_bits(priv->regs, MX25_ADCQ_CFG(reg),
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MX25_ADCQ_CFG_REFP_MASK |
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MX25_ADCQ_CFG_REFN_MASK,
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refp | refn);
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}
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regmap_update_bits(priv->regs, MX25_ADCQ_CR,
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MX25_ADCQ_CR_FRST | MX25_ADCQ_CR_QRST,
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MX25_ADCQ_CR_FRST | MX25_ADCQ_CR_QRST);
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regmap_write(priv->regs, MX25_ADCQ_CR,
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MX25_ADCQ_CR_PDMSK | MX25_ADCQ_CR_QSM_FQS);
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return 0;
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}
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static int mx25_gcq_probe(struct platform_device *pdev)
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{
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struct iio_dev *indio_dev;
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struct mx25_gcq_priv *priv;
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struct mx25_tsadc *tsadc = dev_get_drvdata(pdev->dev.parent);
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struct device *dev = &pdev->dev;
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void __iomem *mem;
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int ret;
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int i;
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indio_dev = devm_iio_device_alloc(dev, sizeof(*priv));
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if (!indio_dev)
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return -ENOMEM;
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priv = iio_priv(indio_dev);
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mem = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(mem))
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return PTR_ERR(mem);
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priv->regs = devm_regmap_init_mmio(dev, mem, &mx25_gcq_regconfig);
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if (IS_ERR(priv->regs)) {
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dev_err(dev, "Failed to initialize regmap\n");
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return PTR_ERR(priv->regs);
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}
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mutex_init(&priv->lock);
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init_completion(&priv->completed);
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ret = mx25_gcq_setup_cfgs(pdev, priv);
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if (ret)
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return ret;
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for (i = 0; i != 4; ++i) {
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if (!priv->vref[i])
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continue;
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ret = regulator_enable(priv->vref[i]);
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if (ret)
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goto err_regulator_disable;
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}
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priv->clk = tsadc->clk;
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ret = clk_prepare_enable(priv->clk);
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if (ret) {
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dev_err(dev, "Failed to enable clock\n");
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goto err_vref_disable;
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}
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ret = platform_get_irq(pdev, 0);
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if (ret < 0)
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goto err_clk_unprepare;
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priv->irq = ret;
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ret = request_irq(priv->irq, mx25_gcq_irq, 0, pdev->name, priv);
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if (ret) {
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dev_err(dev, "Failed requesting IRQ\n");
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goto err_clk_unprepare;
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}
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indio_dev->channels = mx25_gcq_channels;
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indio_dev->num_channels = ARRAY_SIZE(mx25_gcq_channels);
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indio_dev->info = &mx25_gcq_iio_info;
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indio_dev->name = driver_name;
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ret = iio_device_register(indio_dev);
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if (ret) {
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dev_err(dev, "Failed to register iio device\n");
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goto err_irq_free;
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}
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platform_set_drvdata(pdev, indio_dev);
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return 0;
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err_irq_free:
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free_irq(priv->irq, priv);
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err_clk_unprepare:
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clk_disable_unprepare(priv->clk);
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err_vref_disable:
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i = 4;
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err_regulator_disable:
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for (; i-- > 0;) {
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if (priv->vref[i])
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regulator_disable(priv->vref[i]);
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}
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return ret;
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}
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static void mx25_gcq_remove(struct platform_device *pdev)
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{
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struct iio_dev *indio_dev = platform_get_drvdata(pdev);
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struct mx25_gcq_priv *priv = iio_priv(indio_dev);
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int i;
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iio_device_unregister(indio_dev);
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free_irq(priv->irq, priv);
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clk_disable_unprepare(priv->clk);
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for (i = 4; i-- > 0;) {
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if (priv->vref[i])
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regulator_disable(priv->vref[i]);
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}
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}
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static const struct of_device_id mx25_gcq_ids[] = {
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{ .compatible = "fsl,imx25-gcq", },
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{ /* Sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, mx25_gcq_ids);
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static struct platform_driver mx25_gcq_driver = {
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.driver = {
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.name = "mx25-gcq",
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.of_match_table = mx25_gcq_ids,
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},
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.probe = mx25_gcq_probe,
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.remove_new = mx25_gcq_remove,
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};
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module_platform_driver(mx25_gcq_driver);
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MODULE_DESCRIPTION("ADC driver for Freescale mx25");
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MODULE_AUTHOR("Markus Pargmann <mpa@pengutronix.de>");
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MODULE_LICENSE("GPL v2");
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