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![Jonathan Cameron](/assets/img/avatar_default.png)
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Fixes tag is inaccurate but unlikely anyone will be interested in
backporting beyond that point.
Fixes: 53ac8500ba
("staging:iio:adxrs450: Move header file contents to main file")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Acked-by: Nuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-75-jic23@kernel.org
464 lines
11 KiB
C
464 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* ADXRS450/ADXRS453 Digital Output Gyroscope Driver
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*
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* Copyright 2011 Analog Devices Inc.
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*/
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/delay.h>
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#include <linux/mutex.h>
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#include <linux/device.h>
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#include <linux/kernel.h>
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#include <linux/spi/spi.h>
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#include <linux/slab.h>
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#include <linux/sysfs.h>
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#include <linux/list.h>
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#include <linux/module.h>
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#include <linux/iio/iio.h>
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#include <linux/iio/sysfs.h>
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#define ADXRS450_STARTUP_DELAY 50 /* ms */
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/* The MSB for the spi commands */
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#define ADXRS450_SENSOR_DATA (0x20 << 24)
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#define ADXRS450_WRITE_DATA (0x40 << 24)
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#define ADXRS450_READ_DATA (0x80 << 24)
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#define ADXRS450_RATE1 0x00 /* Rate Registers */
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#define ADXRS450_TEMP1 0x02 /* Temperature Registers */
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#define ADXRS450_LOCST1 0x04 /* Low CST Memory Registers */
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#define ADXRS450_HICST1 0x06 /* High CST Memory Registers */
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#define ADXRS450_QUAD1 0x08 /* Quad Memory Registers */
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#define ADXRS450_FAULT1 0x0A /* Fault Registers */
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#define ADXRS450_PID1 0x0C /* Part ID Register 1 */
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#define ADXRS450_SNH 0x0E /* Serial Number Registers, 4 bytes */
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#define ADXRS450_SNL 0x10
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#define ADXRS450_DNC1 0x12 /* Dynamic Null Correction Registers */
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/* Check bits */
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#define ADXRS450_P 0x01
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#define ADXRS450_CHK 0x02
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#define ADXRS450_CST 0x04
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#define ADXRS450_PWR 0x08
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#define ADXRS450_POR 0x10
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#define ADXRS450_NVM 0x20
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#define ADXRS450_Q 0x40
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#define ADXRS450_PLL 0x80
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#define ADXRS450_UV 0x100
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#define ADXRS450_OV 0x200
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#define ADXRS450_AMP 0x400
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#define ADXRS450_FAIL 0x800
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#define ADXRS450_WRERR_MASK (0x7 << 29)
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#define ADXRS450_MAX_RX 4
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#define ADXRS450_MAX_TX 4
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#define ADXRS450_GET_ST(a) ((a >> 26) & 0x3)
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enum {
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ID_ADXRS450,
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ID_ADXRS453,
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};
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/**
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* struct adxrs450_state - device instance specific data
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* @us: actual spi_device
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* @buf_lock: mutex to protect tx and rx
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* @tx: transmit buffer
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* @rx: receive buffer
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**/
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struct adxrs450_state {
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struct spi_device *us;
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struct mutex buf_lock;
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__be32 tx __aligned(IIO_DMA_MINALIGN);
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__be32 rx;
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};
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/**
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* adxrs450_spi_read_reg_16() - read 2 bytes from a register pair
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* @indio_dev: device associated with child of actual iio_dev
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* @reg_address: the address of the lower of the two registers, which should be
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* an even address, the second register's address is reg_address + 1.
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* @val: somewhere to pass back the value read
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**/
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static int adxrs450_spi_read_reg_16(struct iio_dev *indio_dev,
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u8 reg_address,
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u16 *val)
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{
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struct adxrs450_state *st = iio_priv(indio_dev);
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u32 tx;
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int ret;
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struct spi_transfer xfers[] = {
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{
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.tx_buf = &st->tx,
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.bits_per_word = 8,
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.len = sizeof(st->tx),
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.cs_change = 1,
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}, {
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.rx_buf = &st->rx,
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.bits_per_word = 8,
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.len = sizeof(st->rx),
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},
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};
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mutex_lock(&st->buf_lock);
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tx = ADXRS450_READ_DATA | (reg_address << 17);
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if (!(hweight32(tx) & 1))
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tx |= ADXRS450_P;
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st->tx = cpu_to_be32(tx);
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ret = spi_sync_transfer(st->us, xfers, ARRAY_SIZE(xfers));
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if (ret) {
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dev_err(&st->us->dev, "problem while reading 16 bit register 0x%02x\n",
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reg_address);
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goto error_ret;
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}
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*val = (be32_to_cpu(st->rx) >> 5) & 0xFFFF;
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error_ret:
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mutex_unlock(&st->buf_lock);
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return ret;
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}
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/**
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* adxrs450_spi_write_reg_16() - write 2 bytes data to a register pair
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* @indio_dev: device associated with child of actual actual iio_dev
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* @reg_address: the address of the lower of the two registers,which should be
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* an even address, the second register's address is reg_address + 1.
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* @val: value to be written.
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**/
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static int adxrs450_spi_write_reg_16(struct iio_dev *indio_dev,
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u8 reg_address,
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u16 val)
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{
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struct adxrs450_state *st = iio_priv(indio_dev);
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u32 tx;
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int ret;
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mutex_lock(&st->buf_lock);
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tx = ADXRS450_WRITE_DATA | (reg_address << 17) | (val << 1);
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if (!(hweight32(tx) & 1))
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tx |= ADXRS450_P;
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st->tx = cpu_to_be32(tx);
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ret = spi_write(st->us, &st->tx, sizeof(st->tx));
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if (ret)
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dev_err(&st->us->dev, "problem while writing 16 bit register 0x%02x\n",
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reg_address);
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usleep_range(100, 1000); /* enforce sequential transfer delay 0.1ms */
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mutex_unlock(&st->buf_lock);
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return ret;
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}
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/**
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* adxrs450_spi_sensor_data() - read 2 bytes sensor data
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* @indio_dev: device associated with child of actual iio_dev
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* @val: somewhere to pass back the value read
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**/
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static int adxrs450_spi_sensor_data(struct iio_dev *indio_dev, s16 *val)
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{
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struct adxrs450_state *st = iio_priv(indio_dev);
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int ret;
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struct spi_transfer xfers[] = {
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{
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.tx_buf = &st->tx,
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.bits_per_word = 8,
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.len = sizeof(st->tx),
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.cs_change = 1,
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}, {
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.rx_buf = &st->rx,
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.bits_per_word = 8,
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.len = sizeof(st->rx),
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},
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};
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mutex_lock(&st->buf_lock);
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st->tx = cpu_to_be32(ADXRS450_SENSOR_DATA);
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ret = spi_sync_transfer(st->us, xfers, ARRAY_SIZE(xfers));
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if (ret) {
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dev_err(&st->us->dev, "Problem while reading sensor data\n");
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goto error_ret;
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}
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*val = (be32_to_cpu(st->rx) >> 10) & 0xFFFF;
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error_ret:
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mutex_unlock(&st->buf_lock);
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return ret;
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}
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/**
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* adxrs450_spi_initial() - use for initializing procedure.
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* @st: device instance specific data
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* @val: somewhere to pass back the value read
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* @chk: Whether to perform fault check
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**/
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static int adxrs450_spi_initial(struct adxrs450_state *st,
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u32 *val, char chk)
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{
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int ret;
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u32 tx;
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struct spi_transfer xfers = {
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.tx_buf = &st->tx,
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.rx_buf = &st->rx,
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.bits_per_word = 8,
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.len = sizeof(st->tx),
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};
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mutex_lock(&st->buf_lock);
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tx = ADXRS450_SENSOR_DATA;
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if (chk)
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tx |= (ADXRS450_CHK | ADXRS450_P);
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st->tx = cpu_to_be32(tx);
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ret = spi_sync_transfer(st->us, &xfers, 1);
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if (ret) {
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dev_err(&st->us->dev, "Problem while reading initializing data\n");
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goto error_ret;
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}
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*val = be32_to_cpu(st->rx);
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error_ret:
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mutex_unlock(&st->buf_lock);
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return ret;
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}
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/* Recommended Startup Sequence by spec */
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static int adxrs450_initial_setup(struct iio_dev *indio_dev)
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{
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u32 t;
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u16 data;
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int ret;
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struct adxrs450_state *st = iio_priv(indio_dev);
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msleep(ADXRS450_STARTUP_DELAY*2);
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ret = adxrs450_spi_initial(st, &t, 1);
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if (ret)
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return ret;
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if (t != 0x01)
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dev_warn(&st->us->dev, "The initial power on response is not correct! Restart without reset?\n");
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msleep(ADXRS450_STARTUP_DELAY);
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ret = adxrs450_spi_initial(st, &t, 0);
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if (ret)
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return ret;
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msleep(ADXRS450_STARTUP_DELAY);
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ret = adxrs450_spi_initial(st, &t, 0);
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if (ret)
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return ret;
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if (((t & 0xff) | 0x01) != 0xff || ADXRS450_GET_ST(t) != 2) {
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dev_err(&st->us->dev, "The second response is not correct!\n");
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return -EIO;
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}
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ret = adxrs450_spi_initial(st, &t, 0);
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if (ret)
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return ret;
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if (((t & 0xff) | 0x01) != 0xff || ADXRS450_GET_ST(t) != 2) {
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dev_err(&st->us->dev, "The third response is not correct!\n");
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return -EIO;
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}
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ret = adxrs450_spi_read_reg_16(indio_dev, ADXRS450_FAULT1, &data);
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if (ret)
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return ret;
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if (data & 0x0fff) {
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dev_err(&st->us->dev, "The device is not in normal status!\n");
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return -EINVAL;
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}
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return 0;
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}
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static int adxrs450_write_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int val,
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int val2,
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long mask)
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{
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int ret;
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switch (mask) {
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case IIO_CHAN_INFO_CALIBBIAS:
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if (val < -0x400 || val >= 0x400)
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return -EINVAL;
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ret = adxrs450_spi_write_reg_16(indio_dev,
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ADXRS450_DNC1, val);
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break;
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default:
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ret = -EINVAL;
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break;
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}
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return ret;
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}
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static int adxrs450_read_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int *val,
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int *val2,
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long mask)
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{
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int ret;
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s16 t;
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switch (mask) {
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case IIO_CHAN_INFO_RAW:
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switch (chan->type) {
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case IIO_ANGL_VEL:
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ret = adxrs450_spi_sensor_data(indio_dev, &t);
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if (ret)
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break;
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*val = t;
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ret = IIO_VAL_INT;
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break;
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case IIO_TEMP:
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ret = adxrs450_spi_read_reg_16(indio_dev,
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ADXRS450_TEMP1, &t);
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if (ret)
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break;
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*val = (t >> 6) + 225;
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ret = IIO_VAL_INT;
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break;
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default:
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ret = -EINVAL;
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break;
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}
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break;
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case IIO_CHAN_INFO_SCALE:
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switch (chan->type) {
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case IIO_ANGL_VEL:
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*val = 0;
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*val2 = 218166;
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return IIO_VAL_INT_PLUS_NANO;
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case IIO_TEMP:
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*val = 200;
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*val2 = 0;
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return IIO_VAL_INT;
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default:
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return -EINVAL;
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}
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case IIO_CHAN_INFO_QUADRATURE_CORRECTION_RAW:
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ret = adxrs450_spi_read_reg_16(indio_dev, ADXRS450_QUAD1, &t);
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if (ret)
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break;
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*val = t;
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ret = IIO_VAL_INT;
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break;
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case IIO_CHAN_INFO_CALIBBIAS:
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ret = adxrs450_spi_read_reg_16(indio_dev, ADXRS450_DNC1, &t);
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if (ret)
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break;
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*val = sign_extend32(t, 9);
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ret = IIO_VAL_INT;
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break;
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default:
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ret = -EINVAL;
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break;
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}
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return ret;
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}
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static const struct iio_chan_spec adxrs450_channels[2][2] = {
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[ID_ADXRS450] = {
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{
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.type = IIO_ANGL_VEL,
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.modified = 1,
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.channel2 = IIO_MOD_Z,
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
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BIT(IIO_CHAN_INFO_CALIBBIAS) |
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BIT(IIO_CHAN_INFO_QUADRATURE_CORRECTION_RAW) |
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BIT(IIO_CHAN_INFO_SCALE),
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}, {
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.type = IIO_TEMP,
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.indexed = 1,
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.channel = 0,
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
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BIT(IIO_CHAN_INFO_SCALE),
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}
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},
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[ID_ADXRS453] = {
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{
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.type = IIO_ANGL_VEL,
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.modified = 1,
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.channel2 = IIO_MOD_Z,
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
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BIT(IIO_CHAN_INFO_SCALE) |
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BIT(IIO_CHAN_INFO_QUADRATURE_CORRECTION_RAW),
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}, {
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.type = IIO_TEMP,
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.indexed = 1,
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.channel = 0,
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
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BIT(IIO_CHAN_INFO_SCALE),
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}
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},
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};
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static const struct iio_info adxrs450_info = {
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.read_raw = &adxrs450_read_raw,
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.write_raw = &adxrs450_write_raw,
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};
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static int adxrs450_probe(struct spi_device *spi)
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{
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int ret;
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struct adxrs450_state *st;
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struct iio_dev *indio_dev;
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/* setup the industrialio driver allocated elements */
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indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
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if (!indio_dev)
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return -ENOMEM;
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st = iio_priv(indio_dev);
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st->us = spi;
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mutex_init(&st->buf_lock);
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/* This is only used for removal purposes */
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spi_set_drvdata(spi, indio_dev);
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indio_dev->info = &adxrs450_info;
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indio_dev->modes = INDIO_DIRECT_MODE;
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indio_dev->channels =
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adxrs450_channels[spi_get_device_id(spi)->driver_data];
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indio_dev->num_channels = ARRAY_SIZE(adxrs450_channels);
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indio_dev->name = spi->dev.driver->name;
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ret = devm_iio_device_register(&spi->dev, indio_dev);
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if (ret)
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return ret;
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/* Get the device into a sane initial state */
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ret = adxrs450_initial_setup(indio_dev);
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if (ret)
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return ret;
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return 0;
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}
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static const struct spi_device_id adxrs450_id[] = {
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{"adxrs450", ID_ADXRS450},
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{"adxrs453", ID_ADXRS453},
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{}
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};
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MODULE_DEVICE_TABLE(spi, adxrs450_id);
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static struct spi_driver adxrs450_driver = {
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.driver = {
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.name = "adxrs450",
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},
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.probe = adxrs450_probe,
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.id_table = adxrs450_id,
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};
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module_spi_driver(adxrs450_driver);
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MODULE_AUTHOR("Cliff Cai <cliff.cai@xxxxxxxxxx>");
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MODULE_DESCRIPTION("Analog Devices ADXRS450/ADXRS453 Gyroscope SPI driver");
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MODULE_LICENSE("GPL v2");
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