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cff66ace51
The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230714174638.4058268-1-robh@kernel.org Signed-off-by: Georgi Djakov <djakov@kernel.org>
260 lines
6.8 KiB
C
260 lines
6.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Interconnect framework driver for i.MX8MP SoC
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*
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* Copyright 2022 NXP
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* Peng Fan <peng.fan@nxp.com>
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <dt-bindings/interconnect/fsl,imx8mp.h>
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#include "imx.h"
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static const struct imx_icc_node_adj_desc imx8mp_noc_adj = {
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.bw_mul = 1,
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.bw_div = 16,
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.main_noc = true,
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};
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static struct imx_icc_noc_setting noc_setting_nodes[] = {
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[IMX8MP_ICM_MLMIX] = {
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.reg = 0x180,
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.mode = IMX_NOC_MODE_FIXED,
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.prio_level = 3,
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},
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[IMX8MP_ICM_DSP] = {
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.reg = 0x200,
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.mode = IMX_NOC_MODE_FIXED,
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.prio_level = 3,
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},
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[IMX8MP_ICM_SDMA2PER] = {
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.reg = 0x280,
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.mode = IMX_NOC_MODE_FIXED,
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.prio_level = 4,
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},
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[IMX8MP_ICM_SDMA2BURST] = {
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.reg = 0x300,
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.mode = IMX_NOC_MODE_FIXED,
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.prio_level = 4,
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},
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[IMX8MP_ICM_SDMA3PER] = {
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.reg = 0x380,
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.mode = IMX_NOC_MODE_FIXED,
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.prio_level = 4,
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},
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[IMX8MP_ICM_SDMA3BURST] = {
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.reg = 0x400,
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.mode = IMX_NOC_MODE_FIXED,
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.prio_level = 4,
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},
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[IMX8MP_ICM_EDMA] = {
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.reg = 0x480,
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.mode = IMX_NOC_MODE_FIXED,
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.prio_level = 4,
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},
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[IMX8MP_ICM_GPU3D] = {
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.reg = 0x500,
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.mode = IMX_NOC_MODE_FIXED,
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.prio_level = 3,
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},
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[IMX8MP_ICM_GPU2D] = {
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.reg = 0x580,
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.mode = IMX_NOC_MODE_FIXED,
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.prio_level = 3,
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},
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[IMX8MP_ICM_HRV] = {
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.reg = 0x600,
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.mode = IMX_NOC_MODE_FIXED,
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.prio_level = 2,
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.ext_control = 1,
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},
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[IMX8MP_ICM_LCDIF_HDMI] = {
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.reg = 0x680,
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.mode = IMX_NOC_MODE_FIXED,
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.prio_level = 2,
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.ext_control = 1,
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},
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[IMX8MP_ICM_HDCP] = {
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.reg = 0x700,
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.mode = IMX_NOC_MODE_FIXED,
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.prio_level = 5,
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},
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[IMX8MP_ICM_NOC_PCIE] = {
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.reg = 0x780,
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.mode = IMX_NOC_MODE_FIXED,
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.prio_level = 3,
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},
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[IMX8MP_ICM_USB1] = {
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.reg = 0x800,
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.mode = IMX_NOC_MODE_FIXED,
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.prio_level = 3,
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},
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[IMX8MP_ICM_USB2] = {
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.reg = 0x880,
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.mode = IMX_NOC_MODE_FIXED,
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.prio_level = 3,
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},
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[IMX8MP_ICM_PCIE] = {
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.reg = 0x900,
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.mode = IMX_NOC_MODE_FIXED,
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.prio_level = 3,
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},
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[IMX8MP_ICM_LCDIF_RD] = {
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.reg = 0x980,
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.mode = IMX_NOC_MODE_FIXED,
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.prio_level = 2,
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.ext_control = 1,
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},
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[IMX8MP_ICM_LCDIF_WR] = {
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.reg = 0xa00,
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.mode = IMX_NOC_MODE_FIXED,
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.prio_level = 2,
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.ext_control = 1,
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},
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[IMX8MP_ICM_ISI0] = {
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.reg = 0xa80,
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.mode = IMX_NOC_MODE_FIXED,
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.prio_level = 2,
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.ext_control = 1,
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},
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[IMX8MP_ICM_ISI1] = {
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.reg = 0xb00,
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.mode = IMX_NOC_MODE_FIXED,
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.prio_level = 2,
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.ext_control = 1,
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},
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[IMX8MP_ICM_ISI2] = {
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.reg = 0xb80,
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.mode = IMX_NOC_MODE_FIXED,
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.prio_level = 2,
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.ext_control = 1,
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},
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[IMX8MP_ICM_ISP0] = {
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.reg = 0xc00,
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.mode = IMX_NOC_MODE_FIXED,
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.prio_level = 7,
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},
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[IMX8MP_ICM_ISP1] = {
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.reg = 0xc80,
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.mode = IMX_NOC_MODE_FIXED,
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.prio_level = 7,
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},
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[IMX8MP_ICM_DWE] = {
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.reg = 0xd00,
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.mode = IMX_NOC_MODE_FIXED,
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.prio_level = 7,
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},
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[IMX8MP_ICM_VPU_G1] = {
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.reg = 0xd80,
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.mode = IMX_NOC_MODE_FIXED,
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.prio_level = 3,
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},
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[IMX8MP_ICM_VPU_G2] = {
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.reg = 0xe00,
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.mode = IMX_NOC_MODE_FIXED,
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.prio_level = 3,
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},
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[IMX8MP_ICM_VPU_H1] = {
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.reg = 0xe80,
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.mode = IMX_NOC_MODE_FIXED,
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.prio_level = 3,
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},
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[IMX8MP_ICN_MEDIA] = {
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.mode = IMX_NOC_MODE_UNCONFIGURED,
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},
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[IMX8MP_ICN_VIDEO] = {
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.mode = IMX_NOC_MODE_UNCONFIGURED,
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},
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[IMX8MP_ICN_AUDIO] = {
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.mode = IMX_NOC_MODE_UNCONFIGURED,
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},
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[IMX8MP_ICN_HDMI] = {
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.mode = IMX_NOC_MODE_UNCONFIGURED,
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},
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[IMX8MP_ICN_GPU] = {
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.mode = IMX_NOC_MODE_UNCONFIGURED,
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},
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[IMX8MP_ICN_HSIO] = {
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.mode = IMX_NOC_MODE_UNCONFIGURED,
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},
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};
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/* Describe bus masters, slaves and connections between them */
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static struct imx_icc_node_desc nodes[] = {
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DEFINE_BUS_INTERCONNECT("NOC", IMX8MP_ICN_NOC, &imx8mp_noc_adj,
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IMX8MP_ICS_DRAM, IMX8MP_ICN_MAIN),
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DEFINE_BUS_SLAVE("OCRAM", IMX8MP_ICS_OCRAM, NULL),
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DEFINE_BUS_SLAVE("DRAM", IMX8MP_ICS_DRAM, NULL),
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DEFINE_BUS_MASTER("A53", IMX8MP_ICM_A53, IMX8MP_ICN_NOC),
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DEFINE_BUS_MASTER("SUPERMIX", IMX8MP_ICM_SUPERMIX, IMX8MP_ICN_NOC),
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DEFINE_BUS_MASTER("GIC", IMX8MP_ICM_GIC, IMX8MP_ICN_NOC),
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DEFINE_BUS_MASTER("MLMIX", IMX8MP_ICM_MLMIX, IMX8MP_ICN_NOC),
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DEFINE_BUS_INTERCONNECT("NOC_AUDIO", IMX8MP_ICN_AUDIO, NULL, IMX8MP_ICN_NOC),
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DEFINE_BUS_MASTER("DSP", IMX8MP_ICM_DSP, IMX8MP_ICN_AUDIO),
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DEFINE_BUS_MASTER("SDMA2PER", IMX8MP_ICM_SDMA2PER, IMX8MP_ICN_AUDIO),
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DEFINE_BUS_MASTER("SDMA2BURST", IMX8MP_ICM_SDMA2BURST, IMX8MP_ICN_AUDIO),
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DEFINE_BUS_MASTER("SDMA3PER", IMX8MP_ICM_SDMA3PER, IMX8MP_ICN_AUDIO),
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DEFINE_BUS_MASTER("SDMA3BURST", IMX8MP_ICM_SDMA3BURST, IMX8MP_ICN_AUDIO),
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DEFINE_BUS_MASTER("EDMA", IMX8MP_ICM_EDMA, IMX8MP_ICN_AUDIO),
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DEFINE_BUS_INTERCONNECT("NOC_GPU", IMX8MP_ICN_GPU, NULL, IMX8MP_ICN_NOC),
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DEFINE_BUS_MASTER("GPU 2D", IMX8MP_ICM_GPU2D, IMX8MP_ICN_GPU),
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DEFINE_BUS_MASTER("GPU 3D", IMX8MP_ICM_GPU3D, IMX8MP_ICN_GPU),
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DEFINE_BUS_INTERCONNECT("NOC_HDMI", IMX8MP_ICN_HDMI, NULL, IMX8MP_ICN_NOC),
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DEFINE_BUS_MASTER("HRV", IMX8MP_ICM_HRV, IMX8MP_ICN_HDMI),
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DEFINE_BUS_MASTER("LCDIF_HDMI", IMX8MP_ICM_LCDIF_HDMI, IMX8MP_ICN_HDMI),
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DEFINE_BUS_MASTER("HDCP", IMX8MP_ICM_HDCP, IMX8MP_ICN_HDMI),
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DEFINE_BUS_INTERCONNECT("NOC_HSIO", IMX8MP_ICN_HSIO, NULL, IMX8MP_ICN_NOC),
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DEFINE_BUS_MASTER("NOC_PCIE", IMX8MP_ICM_NOC_PCIE, IMX8MP_ICN_HSIO),
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DEFINE_BUS_MASTER("USB1", IMX8MP_ICM_USB1, IMX8MP_ICN_HSIO),
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DEFINE_BUS_MASTER("USB2", IMX8MP_ICM_USB2, IMX8MP_ICN_HSIO),
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DEFINE_BUS_MASTER("PCIE", IMX8MP_ICM_PCIE, IMX8MP_ICN_HSIO),
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DEFINE_BUS_INTERCONNECT("NOC_MEDIA", IMX8MP_ICN_MEDIA, NULL, IMX8MP_ICN_NOC),
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DEFINE_BUS_MASTER("LCDIF_RD", IMX8MP_ICM_LCDIF_RD, IMX8MP_ICN_MEDIA),
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DEFINE_BUS_MASTER("LCDIF_WR", IMX8MP_ICM_LCDIF_WR, IMX8MP_ICN_MEDIA),
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DEFINE_BUS_MASTER("ISI0", IMX8MP_ICM_ISI0, IMX8MP_ICN_MEDIA),
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DEFINE_BUS_MASTER("ISI1", IMX8MP_ICM_ISI1, IMX8MP_ICN_MEDIA),
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DEFINE_BUS_MASTER("ISI2", IMX8MP_ICM_ISI2, IMX8MP_ICN_MEDIA),
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DEFINE_BUS_MASTER("ISP0", IMX8MP_ICM_ISP0, IMX8MP_ICN_MEDIA),
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DEFINE_BUS_MASTER("ISP1", IMX8MP_ICM_ISP1, IMX8MP_ICN_MEDIA),
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DEFINE_BUS_MASTER("DWE", IMX8MP_ICM_DWE, IMX8MP_ICN_MEDIA),
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DEFINE_BUS_INTERCONNECT("NOC_VIDEO", IMX8MP_ICN_VIDEO, NULL, IMX8MP_ICN_NOC),
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DEFINE_BUS_MASTER("VPU G1", IMX8MP_ICM_VPU_G1, IMX8MP_ICN_VIDEO),
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DEFINE_BUS_MASTER("VPU G2", IMX8MP_ICM_VPU_G2, IMX8MP_ICN_VIDEO),
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DEFINE_BUS_MASTER("VPU H1", IMX8MP_ICM_VPU_H1, IMX8MP_ICN_VIDEO),
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DEFINE_BUS_INTERCONNECT("PL301_MAIN", IMX8MP_ICN_MAIN, NULL,
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IMX8MP_ICN_NOC, IMX8MP_ICS_OCRAM),
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};
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static int imx8mp_icc_probe(struct platform_device *pdev)
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{
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return imx_icc_register(pdev, nodes, ARRAY_SIZE(nodes), noc_setting_nodes);
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}
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static int imx8mp_icc_remove(struct platform_device *pdev)
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{
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imx_icc_unregister(pdev);
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return 0;
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}
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static struct platform_driver imx8mp_icc_driver = {
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.probe = imx8mp_icc_probe,
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.remove = imx8mp_icc_remove,
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.driver = {
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.name = "imx8mp-interconnect",
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},
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};
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module_platform_driver(imx8mp_icc_driver);
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MODULE_AUTHOR("Peng Fan <peng.fan@nxp.com>");
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MODULE_LICENSE("GPL");
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MODULE_ALIAS("platform:imx8mp-interconnect");
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