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We currently use 64bit I/O on the 32bit registers. This works because there are an even number of assert and status registers, so they're only ever accessed in pairs on 64bit boundaries. There are however other reset controllers for audio and video on the JH7100 SoC with only one status register that isn't 64bit aligned so 64bit I/O results in an unaligned access exception. Switch to 32bit I/O in preparation for supporting these resets too. Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
74 lines
2 KiB
C
74 lines
2 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Reset driver for the StarFive JH7100 SoC
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*
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* Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
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*/
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#include <linux/mod_devicetable.h>
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#include <linux/platform_device.h>
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#include "reset-starfive-jh71x0.h"
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#include <dt-bindings/reset/starfive-jh7100.h>
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/* register offsets */
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#define JH7100_RESET_ASSERT0 0x00
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#define JH7100_RESET_ASSERT1 0x04
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#define JH7100_RESET_ASSERT2 0x08
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#define JH7100_RESET_ASSERT3 0x0c
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#define JH7100_RESET_STATUS0 0x10
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#define JH7100_RESET_STATUS1 0x14
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#define JH7100_RESET_STATUS2 0x18
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#define JH7100_RESET_STATUS3 0x1c
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/*
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* Writing a 1 to the n'th bit of the m'th ASSERT register asserts
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* line 32m + n, and writing a 0 deasserts the same line.
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* Most reset lines have their status inverted so a 0 bit in the STATUS
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* register means the line is asserted and a 1 means it's deasserted. A few
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* lines don't though, so store the expected value of the status registers when
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* all lines are asserted.
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*/
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static const u32 jh7100_reset_asserted[4] = {
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/* STATUS0 */
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BIT(JH7100_RST_U74 % 32) |
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BIT(JH7100_RST_VP6_DRESET % 32) |
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BIT(JH7100_RST_VP6_BRESET % 32),
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/* STATUS1 */
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BIT(JH7100_RST_HIFI4_DRESET % 32) |
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BIT(JH7100_RST_HIFI4_BRESET % 32),
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/* STATUS2 */
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BIT(JH7100_RST_E24 % 32),
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/* STATUS3 */
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0,
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};
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static int __init jh7100_reset_probe(struct platform_device *pdev)
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{
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void __iomem *base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(base))
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return PTR_ERR(base);
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return reset_starfive_jh71x0_register(&pdev->dev, pdev->dev.of_node,
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base + JH7100_RESET_ASSERT0,
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base + JH7100_RESET_STATUS0,
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jh7100_reset_asserted,
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JH7100_RSTN_END,
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THIS_MODULE);
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}
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static const struct of_device_id jh7100_reset_dt_ids[] = {
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{ .compatible = "starfive,jh7100-reset" },
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{ /* sentinel */ }
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};
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static struct platform_driver jh7100_reset_driver = {
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.driver = {
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.name = "jh7100-reset",
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.of_match_table = jh7100_reset_dt_ids,
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.suppress_bind_attrs = true,
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},
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};
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builtin_platform_driver_probe(jh7100_reset_driver, jh7100_reset_probe);
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