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b6d7406cd7
We currently use 64bit I/O on the 32bit registers. This works because there are an even number of assert and status registers, so they're only ever accessed in pairs on 64bit boundaries. There are however other reset controllers for audio and video on the JH7100 SoC with only one status register that isn't 64bit aligned so 64bit I/O results in an unaligned access exception. Switch to 32bit I/O in preparation for supporting these resets too. Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
131 lines
3.3 KiB
C
131 lines
3.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Reset driver for the StarFive JH71X0 SoCs
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*
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* Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
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*/
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#include <linux/bitmap.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/reset-controller.h>
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#include <linux/spinlock.h>
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#include "reset-starfive-jh71x0.h"
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struct jh71x0_reset {
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struct reset_controller_dev rcdev;
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/* protect registers against concurrent read-modify-write */
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spinlock_t lock;
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void __iomem *assert;
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void __iomem *status;
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const u32 *asserted;
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};
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static inline struct jh71x0_reset *
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jh71x0_reset_from(struct reset_controller_dev *rcdev)
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{
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return container_of(rcdev, struct jh71x0_reset, rcdev);
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}
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static int jh71x0_reset_update(struct reset_controller_dev *rcdev,
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unsigned long id, bool assert)
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{
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struct jh71x0_reset *data = jh71x0_reset_from(rcdev);
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unsigned long offset = id / 32;
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u32 mask = BIT(id % 32);
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void __iomem *reg_assert = data->assert + offset * sizeof(u32);
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void __iomem *reg_status = data->status + offset * sizeof(u32);
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u32 done = data->asserted ? data->asserted[offset] & mask : 0;
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u32 value;
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unsigned long flags;
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int ret;
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if (!assert)
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done ^= mask;
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spin_lock_irqsave(&data->lock, flags);
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value = readl(reg_assert);
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if (assert)
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value |= mask;
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else
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value &= ~mask;
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writel(value, reg_assert);
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/* if the associated clock is gated, deasserting might otherwise hang forever */
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ret = readl_poll_timeout_atomic(reg_status, value, (value & mask) == done, 0, 1000);
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spin_unlock_irqrestore(&data->lock, flags);
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return ret;
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}
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static int jh71x0_reset_assert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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return jh71x0_reset_update(rcdev, id, true);
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}
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static int jh71x0_reset_deassert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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return jh71x0_reset_update(rcdev, id, false);
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}
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static int jh71x0_reset_reset(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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int ret;
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ret = jh71x0_reset_assert(rcdev, id);
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if (ret)
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return ret;
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return jh71x0_reset_deassert(rcdev, id);
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}
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static int jh71x0_reset_status(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct jh71x0_reset *data = jh71x0_reset_from(rcdev);
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unsigned long offset = id / 32;
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u32 mask = BIT(id % 32);
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void __iomem *reg_status = data->status + offset * sizeof(u32);
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u32 value = readl(reg_status);
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return !((value ^ data->asserted[offset]) & mask);
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}
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static const struct reset_control_ops jh71x0_reset_ops = {
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.assert = jh71x0_reset_assert,
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.deassert = jh71x0_reset_deassert,
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.reset = jh71x0_reset_reset,
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.status = jh71x0_reset_status,
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};
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int reset_starfive_jh71x0_register(struct device *dev, struct device_node *of_node,
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void __iomem *assert, void __iomem *status,
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const u32 *asserted, unsigned int nr_resets,
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struct module *owner)
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{
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struct jh71x0_reset *data;
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data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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data->rcdev.ops = &jh71x0_reset_ops;
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data->rcdev.owner = owner;
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data->rcdev.nr_resets = nr_resets;
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data->rcdev.dev = dev;
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data->rcdev.of_node = of_node;
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spin_lock_init(&data->lock);
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data->assert = assert;
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data->status = status;
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data->asserted = asserted;
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return devm_reset_controller_register(dev, &data->rcdev);
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}
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EXPORT_SYMBOL_GPL(reset_starfive_jh71x0_register);
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