Jinyu Tang 1b52861f0e riscv: support update_mmu_tlb() ... Add macro definition to support update_mmu_tlb() for riscv, this function is from commit:7df676974359 ("mm/memory.c:Update local TLB if PTE entry exists"). update_mmu_tlb() is used when a thread notice that other cpu thread has handled the fault and changed the PTE. For MIPS, it's worth to do that,this cpu thread will trap in tlb fault again otherwise. For RISCV, it's also better to flush local tlb than do nothing in update_mmu_tlb(). There are two kinds of page fault that have update_mmu_tlb() inside: 1.page fault which PTE is NOT none, only protection check error, like write protection fault. If updata_mmu_tlb() is empty, after finsh page fault this time and re-execute, cpu will find address but protection checked error in tlb again. So this will cause another page fault. PTE in memory is good now,so update_mmu_cache() in handle_pte_fault() will be executed. If updata_mmu_tlb() is not empty flush local tlb, cpu won't find this address in tlb next time, and get entry in physical memory, so it won't cause another page fault. 2.page fault which PTE is none or swapped. For this case, this cpu thread won't cause another page fault,cpu will have tlb miss when re-execute, and get entry in memory directly. But "set pte in phycial memory and flush local tlb" is pratice in Linux, it's better to flush local tlb if it find entry in phycial memory has changed. Maybe it's same for other ARCH which can't detect PTE changed and update it in local tlb automatically. Signed-off-by: Jinyu Tang <tjytimi@163.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Link: https://lore.kernel.org/r/20221009134503.18783-1-tjytimi@163.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>		2022-10-28 12:43:02 -07:00
..
boot	RISC-V Patches for the 6.1 Merge Window, Part 2	2022-10-14 11:21:11 -07:00
configs	riscv: enable CD-ROM file systems in defconfig	2022-08-25 17:01:09 -07:00
errata	drivers/perf: riscv_pmu_sbi: add support for PMU variant on T-Head C9xx cores	2022-10-27 14:35:20 -07:00
include	riscv: support update_mmu_tlb()	2022-10-28 12:43:02 -07:00
kernel	RISC-V: Cache SBI vendor values	2022-10-27 14:35:11 -07:00
kvm	The first batch of KVM patches, mostly covering x86, which I	2022-10-09 09:39:55 -07:00
lib	riscv: lib: uaccess: fix CSR_STATUS SR_SUM bit	2022-08-10 14:06:31 -07:00
mm	RISC-V Patches for the 6.1 Merge Window, Part 2	2022-10-14 11:21:11 -07:00
net	bpf, riscv: Support riscv jit to provide bpf_line_info	2022-06-02 16:26:01 -07:00
purgatory	riscv/purgatory: Omit use of bin2c	2022-08-11 09:32:34 -07:00
Kbuild	riscv: move errata/ and kvm/ builds to arch/riscv/Kbuild	2022-06-01 22:26:32 -07:00
Kconfig	RISC-V Patches for the 6.1 Merge Window, Part 2	2022-10-14 11:21:11 -07:00
Kconfig.debug
Kconfig.erratas	drivers/perf: riscv_pmu_sbi: add support for PMU variant on T-Head C9xx cores	2022-10-27 14:35:20 -07:00
Kconfig.socs	riscv: Kconfig: Style cleanups	2022-06-30 19:26:16 -07:00
Makefile	RISC-V Patches for the 6.1 Merge Window, Part 2	2022-10-14 11:21:11 -07:00