493 lines
23 KiB
JSON
493 lines
23 KiB
JSON
[
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{
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"Unit": "CPU-M-CF",
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"EventCode": "128",
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"EventName": "L1D_RO_EXCL_WRITES",
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"BriefDescription": "L1D Read-only Exclusive Writes",
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"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "129",
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"EventName": "DTLB2_WRITES",
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"BriefDescription": "DTLB2 Writes",
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"PublicDescription": "A translation has been written into The Translation Lookaside Buffer 2 (TLB2) and the request was made by the Level-1 Data cache. This is a replacement for what was provided for the DTLB on z13 and prior machines."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "130",
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"EventName": "DTLB2_MISSES",
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"BriefDescription": "DTLB2 Misses",
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"PublicDescription": "A TLB2 miss is in progress for a request made by the Level-1 Data cache. Incremented by one for every TLB2 miss in progress for the Level-1 Data cache on this cycle. This is a replacement for what was provided for the DTLB on z13 and prior machines."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "131",
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"EventName": "CRSTE_1MB_WRITES",
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"BriefDescription": "One Megabyte CRSTE writes",
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"PublicDescription": "A translation entry was written into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "132",
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"EventName": "DTLB2_GPAGE_WRITES",
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"BriefDescription": "DTLB2 Two-Gigabyte Page Writes",
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"PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "134",
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"EventName": "ITLB2_WRITES",
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"BriefDescription": "ITLB2 Writes",
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"PublicDescription": "A translation entry has been written into the Translation Lookaside Buffer 2 (TLB2) and the request was made by the instruction cache. This is a replacement for what was provided for the ITLB on z13 and prior machines."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "135",
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"EventName": "ITLB2_MISSES",
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"BriefDescription": "ITLB2 Misses",
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"PublicDescription": "A TLB2 miss is in progress for a request made by the Level-1 Instruction cache. Incremented by one for every TLB2 miss in progress for the Level-1 Instruction cache in a cycle. This is a replacement for what was provided for the ITLB on z13 and prior machines."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "137",
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"EventName": "TLB2_PTE_WRITES",
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"BriefDescription": "TLB2 Page Table Entry Writes",
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"PublicDescription": "A translation entry was written into the Page Table Entry array in the Level-2 TLB."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "138",
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"EventName": "TLB2_CRSTE_WRITES",
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"BriefDescription": "TLB2 Combined Region and Segment Entry Writes",
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"PublicDescription": "Translation entries were written into the Combined Region and Segment Table Entry array and the Page Table Entry array in the Level-2 TLB."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "139",
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"EventName": "TLB2_ENGINES_BUSY",
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"BriefDescription": "TLB2 Engines Busy",
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"PublicDescription": "The number of Level-2 TLB translation engines busy in a cycle."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "140",
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"EventName": "TX_C_TEND",
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"BriefDescription": "Completed TEND instructions in constrained TX mode",
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"PublicDescription": "A TEND instruction has completed in a constrained transactional-execution mode."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "141",
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"EventName": "TX_NC_TEND",
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"BriefDescription": "Completed TEND instructions in non-constrained TX mode",
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"PublicDescription": "A TEND instruction has completed in a non-constrained transactional-execution mode."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "143",
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"EventName": "L1C_TLB2_MISSES",
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"BriefDescription": "L1C TLB2 Misses",
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"PublicDescription": "Increments by one for any cycle where a level-1 cache or level-2 TLB miss is in progress."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "145",
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"EventName": "DCW_REQ",
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"BriefDescription": "Directory Write Level 1 Data Cache from L2-Cache",
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"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestors Level-2 cache."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "146",
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"EventName": "DCW_REQ_IV",
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"BriefDescription": "Directory Write Level 1 Data Cache from L2-Cache with Intervention",
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"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestors Level-2 cache with intervention."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "147",
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"EventName": "DCW_REQ_CHIP_HIT",
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"BriefDescription": "Directory Write Level 1 Data Cache from L2-Cache with Chip HP Hit",
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"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestors Level-2 cache after using chip level horizontal persistence, Chip-HP hit."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "148",
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"EventName": "DCW_REQ_DRAWER_HIT",
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"BriefDescription": "Directory Write Level 1 Data Cache from L2-Cache with Drawer HP Hit",
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"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestors Level-2 cache after using drawer level horizontal persistence, Drawer-HP hit."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "149",
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"EventName": "DCW_ON_CHIP",
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"BriefDescription": "Directory Write Level 1 Data Cache from On-Chip L2-Cache",
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"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-2 cache."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "150",
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"EventName": "DCW_ON_CHIP_IV",
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"BriefDescription": "Directory Write Level 1 Data Cache from On-Chip L2-Cache with Intervention",
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"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-2 cache with intervention."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "151",
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"EventName": "DCW_ON_CHIP_CHIP_HIT",
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"BriefDescription": "Directory Write Level 1 Data Cache from On-Chip L2-Cache with Chip HP Hit",
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"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-2 cache after using chip level horizontal persistence, Chip-HP hit."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "152",
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"EventName": "DCW_ON_CHIP_DRAWER_HIT",
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"BriefDescription": "Directory Write Level 1 Data Cache from On-Chip L2-Cache with Drawer HP Hit",
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"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-2 cache using drawer level horizontal persistence, Drawer-HP hit."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "153",
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"EventName": "DCW_ON_MODULE",
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"BriefDescription": "Directory Write Level 1 Data Cache from On-Module L2-Cache",
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"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Module Level-2 cache."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "154",
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"EventName": "DCW_ON_DRAWER",
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"BriefDescription": "Directory Write Level 1 Data Cache from On-Drawer L2-Cache",
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"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Drawer Level-2 cache."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "155",
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"EventName": "DCW_OFF_DRAWER",
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"BriefDescription": "Directory Write Level 1 Data Cache from Off-Drawer L2-Cache",
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"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Level-2 cache."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "156",
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"EventName": "DCW_ON_CHIP_MEMORY",
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"BriefDescription": "Directory Write Level 1 Data Cache from On-Chip Memory",
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"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Chip memory."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "157",
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"EventName": "DCW_ON_MODULE_MEMORY",
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"BriefDescription": "Directory Write Level 1 Data Cache from On-Module Memory",
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"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Module memory."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "158",
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"EventName": "DCW_ON_DRAWER_MEMORY",
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"BriefDescription": "Directory Write Level 1 Data Cache from On-Drawer Memory",
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"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Drawer memory."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "159",
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"EventName": "DCW_OFF_DRAWER_MEMORY",
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"BriefDescription": "Directory Write Level 1 Data Cache from Off-Drawer Memory",
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"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Drawer memory."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "160",
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"EventName": "IDCW_ON_MODULE_IV",
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"BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Module Memory L2-Cache with Intervention",
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"PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an On-Module Level-2 cache with intervention."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "161",
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"EventName": "IDCW_ON_MODULE_CHIP_HIT",
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"BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Module Memory L2-Cache with Chip Hit",
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"PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an On-Module Level-2 cache using chip horizontal persistence, Chip-HP hit."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "162",
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"EventName": "IDCW_ON_MODULE_DRAWER_HIT",
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"BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Module Memory L2-Cache with Drawer Hit",
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"PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an On-Module Level-2 cache using drawer level horizontal persistence, Drawer-HP hit."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "163",
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"EventName": "IDCW_ON_DRAWER_IV",
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"BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Drawer L2-Cache with Intervention",
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"PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an On-Drawer Level-2 cache with intervention."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "164",
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"EventName": "IDCW_ON_DRAWER_CHIP_HIT",
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"BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Drawer L2-Cache with Chip Hit",
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"PublicDescription": "A directory write to the Level-1 Data or Level-1 instruction cache directory where the returned cache line was sourced from an On-Drawer Level-2 cache using chip level horizontal persistence, Chip-HP hit."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "165",
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"EventName": "IDCW_ON_DRAWER_DRAWER_HIT",
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"BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Drawer L2-Cache with Drawer Hit",
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"PublicDescription": "A directory write to the Level-1 Data or Level-1 instruction cache directory where the returned cache line was sourced from an On-Drawer Level-2 cache using drawer level horizontal persistence, Drawer-HP hit."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "166",
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"EventName": "IDCW_OFF_DRAWER_IV",
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"BriefDescription": "Directory Write Level 1 Instruction and Data Cache from Off-Drawer L2-Cache with Intervention",
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"PublicDescription": "A directory write to the Level-1 Data or Level-1 instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-2 cache with intervention."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "167",
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"EventName": "IDCW_OFF_DRAWER_CHIP_HIT",
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"BriefDescription": "Directory Write Level 1 Instruction and Data Cache from Off-Drawer L2-Cache with Chip Hit",
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"PublicDescription": "A directory write to the Level-1 Data or Level-1 instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-2 cache using chip level horizontal persistence, Chip-HP hit."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "168",
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"EventName": "IDCW_OFF_DRAWER_DRAWER_HIT",
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"BriefDescription": "Directory Write Level 1 Instruction and Data Cache from Off-Drawer L2-Cache with Drawer Hit",
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"PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-2 cache using drawer level horizontal persistence, Drawer-HP hit."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "169",
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"EventName": "ICW_REQ",
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"BriefDescription": "Directory Write Level 1 Instruction Cache from L2-Cache",
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"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced the requestors Level-2 cache."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "170",
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"EventName": "ICW_REQ_IV",
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"BriefDescription": "Directory Write Level 1 Instruction Cache from L2-Cache with Intervention",
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"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the requestors Level-2 cache with intervention."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "171",
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"EventName": "ICW_REQ_CHIP_HIT",
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"BriefDescription": "Directory Write Level 1 Instruction Cache from L2-Cache with Chip HP Hit",
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"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the requestors Level-2 cache using chip level horizontal persistence, Chip-HP hit."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "172",
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"EventName": "ICW_REQ_DRAWER_HIT",
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"BriefDescription": "Directory Write Level 1 Instruction Cache from L2-Cache with Drawer HP Hit",
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"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the requestors Level-2 cache using drawer level horizontal persistence, Drawer-HP hit."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "173",
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"EventName": "ICW_ON_CHIP",
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"BriefDescription": "Directory Write Level 1 Instruction Cache from On-Chip L2-Cache",
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"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Chip Level-2 cache."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "174",
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"EventName": "ICW_ON_CHIP_IV",
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"BriefDescription": "Directory Write Level 1 Instruction Cache from On-Chip L2-Cache with Intervention",
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"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced an On-Chip Level-2 cache with intervention."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "175",
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"EventName": "ICW_ON_CHIP_CHIP_HIT",
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"BriefDescription": "Directory Write Level 1 Instruction Cache from On-Chip L2-Cache with Chip HP Hit",
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"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Chip Level-2 cache using chip level horizontal persistence, Chip-HP hit."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "176",
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"EventName": "ICW_ON_CHIP_DRAWER_HIT",
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"BriefDescription": "Directory Write Level 1 Instruction Cache from On-Chip L2-Cache with Drawer HP Hit",
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"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Chip level 2 cache using drawer level horizontal persistence, Drawer-HP hit."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "177",
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"EventName": "ICW_ON_MODULE",
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"BriefDescription": "Directory Write Level 1 Instruction Cache from On-Module L2-Cache",
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"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Module Level-2 cache."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "178",
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"EventName": "ICW_ON_DRAWER",
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"BriefDescription": "Directory Write Level 1 Instruction Cache from On-Drawer L2-Cache",
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"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced an On-Drawer Level-2 cache."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "179",
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"EventName": "ICW_OFF_DRAWER",
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"BriefDescription": "Directory Write Level 1 Instruction Cache from Off-Drawer L2-Cache",
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"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced an Off-Drawer Level-2 cache."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "180",
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"EventName": "ICW_ON_CHIP_MEMORY",
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"BriefDescription": "Directory Write Level 1 Instruction Cache from On-Chip Memory",
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"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Chip memory."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "181",
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"EventName": "ICW_ON_MODULE_MEMORY",
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"BriefDescription": "Directory Write Level 1 Instruction Cache from On-Module Memory",
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"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Module memory."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "182",
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"EventName": "ICW_ON_DRAWER_MEMORY",
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"BriefDescription": "Directory Write Level 1 Instruction Cache from On-Drawer Memory",
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"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Drawer memory."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "183",
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"EventName": "ICW_OFF_DRAWER_MEMORY",
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"BriefDescription": "Directory Write Level 1 Instruction Cache from Off-Drawer Memory",
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"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from Off-Drawer memory."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "224",
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"EventName": "BCD_DFP_EXECUTION_SLOTS",
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"BriefDescription": "Binary Coded Decimal to Decimal Floating Point conversions",
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"PublicDescription": "Count of floating point execution slots used for finished Binary Coded Decimal to Decimal Floating Point conversions. Instructions: CDZT, CXZT, CZDT, CZXT."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "225",
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"EventName": "VX_BCD_EXECUTION_SLOTS",
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"BriefDescription": "Count finished vector arithmetic Binary Coded Decimal instructions",
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"PublicDescription": "Count of floating point execution slots used for finished vector arithmetic Binary Coded Decimal instructions. Instructions: VAP, VSP, VMP, VMSP, VDP, VSDP, VRP, VLIP, VSRP, VPSOP, VCP, VTP, VPKZ, VUPKZ, VCVB, VCVBG, VCVD, VCVDG."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "226",
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"EventName": "DECIMAL_INSTRUCTIONS",
|
|
"BriefDescription": "Decimal instruction dispatched",
|
|
"PublicDescription": "Decimal instruction dispatched. Instructions: CVB, CVD, AP, CP, DP, ED, EDMK, MP, SRP, SP, ZAP."
|
|
},
|
|
{
|
|
"Unit": "CPU-M-CF",
|
|
"EventCode": "232",
|
|
"EventName": "LAST_HOST_TRANSLATIONS",
|
|
"BriefDescription": "Last host translation done",
|
|
"PublicDescription": "Last Host Translation done"
|
|
},
|
|
{
|
|
"Unit": "CPU-M-CF",
|
|
"EventCode": "244",
|
|
"EventName": "TX_NC_TABORT",
|
|
"BriefDescription": "Aborted transactions in unconstrained TX mode",
|
|
"PublicDescription": "A transaction abort has occurred in a non-constrained transactional-execution mode."
|
|
},
|
|
{
|
|
"Unit": "CPU-M-CF",
|
|
"EventCode": "245",
|
|
"EventName": "TX_C_TABORT_NO_SPECIAL",
|
|
"BriefDescription": "Aborted transactions in constrained TX mode",
|
|
"PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is not using any special logic to allow the transaction to complete."
|
|
},
|
|
{
|
|
"Unit": "CPU-M-CF",
|
|
"EventCode": "246",
|
|
"EventName": "TX_C_TABORT_SPECIAL",
|
|
"BriefDescription": "Aborted transactions in constrained TX mode using special completion logic",
|
|
"PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is using special logic to allow the transaction to complete."
|
|
},
|
|
{
|
|
"Unit": "CPU-M-CF",
|
|
"EventCode": "248",
|
|
"EventName": "DFLT_ACCESS",
|
|
"BriefDescription": "Cycles CPU spent obtaining access to Deflate unit",
|
|
"PublicDescription": "Cycles CPU spent obtaining access to Deflate unit"
|
|
},
|
|
{
|
|
"Unit": "CPU-M-CF",
|
|
"EventCode": "253",
|
|
"EventName": "DFLT_CYCLES",
|
|
"BriefDescription": "Cycles CPU is using Deflate unit",
|
|
"PublicDescription": "Cycles CPU is using Deflate unit"
|
|
},
|
|
{
|
|
"Unit": "CPU-M-CF",
|
|
"EventCode": "256",
|
|
"EventName": "SORTL",
|
|
"BriefDescription": "Count SORTL instructions",
|
|
"PublicDescription": "Increments by one for every SORT LISTS instruction executed."
|
|
},
|
|
{
|
|
"Unit": "CPU-M-CF",
|
|
"EventCode": "265",
|
|
"EventName": "DFLT_CC",
|
|
"BriefDescription": "Increments DEFLATE CONVERSION CALL",
|
|
"PublicDescription": "Increments by one for every DEFLATE CONVERSION CALL instruction executed."
|
|
},
|
|
{
|
|
"Unit": "CPU-M-CF",
|
|
"EventCode": "266",
|
|
"EventName": "DFLT_CCFINISH",
|
|
"BriefDescription": "Increments completed DEFLATE CONVERSION CALL",
|
|
"PublicDescription": "Increments by one for every DEFLATE CONVERSION CALL instruction executed that ended in Condition Codes 0, 1 or 2."
|
|
},
|
|
{
|
|
"Unit": "CPU-M-CF",
|
|
"EventCode": "267",
|
|
"EventName": "NNPA_INVOCATIONS",
|
|
"BriefDescription": "NNPA Total invocations",
|
|
"PublicDescription": "Increments by one for every Neural Network Processing Assist instruction executed."
|
|
},
|
|
{
|
|
"Unit": "CPU-M-CF",
|
|
"EventCode": "268",
|
|
"EventName": "NNPA_COMPLETIONS",
|
|
"BriefDescription": "NNPA Total completions",
|
|
"PublicDescription": "Increments by one for every Neural Network Processing Assist instruction executed that ended in Condition Codes 0, 1 or 2."
|
|
},
|
|
{
|
|
"Unit": "CPU-M-CF",
|
|
"EventCode": "269",
|
|
"EventName": "NNPA_WAIT_LOCK",
|
|
"BriefDescription": "Cycles spent obtaining NNPA lock",
|
|
"PublicDescription": "Cycles CPU spent obtaining access to IBM Z Integrated Accelerator for AI."
|
|
},
|
|
{
|
|
"Unit": "CPU-M-CF",
|
|
"EventCode": "270",
|
|
"EventName": "NNPA_HOLD_LOCK",
|
|
"BriefDescription": "Cycles spent holding NNPA lock",
|
|
"PublicDescription": "Cycles CPU is using IBM Z Integrated Accelerator for AI."
|
|
},
|
|
{
|
|
"Unit": "CPU-M-CF",
|
|
"EventCode": "448",
|
|
"EventName": "MT_DIAG_CYCLES_ONE_THR_ACTIVE",
|
|
"BriefDescription": "Cycle count with one thread active",
|
|
"PublicDescription": "Cycle count with one thread active"
|
|
},
|
|
{
|
|
"Unit": "CPU-M-CF",
|
|
"EventCode": "449",
|
|
"EventName": "MT_DIAG_CYCLES_TWO_THR_ACTIVE",
|
|
"BriefDescription": "Cycle count with two threads active",
|
|
"PublicDescription": "Cycle count with two threads active"
|
|
}
|
|
]
|