176 lines
13 KiB
JSON
176 lines
13 KiB
JSON
[
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{
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"BriefDescription": "ARITH.FPDIV_ACTIVE",
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"CounterMask": "1",
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"EventCode": "0xb0",
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"EventName": "ARITH.FPDIV_ACTIVE",
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"SampleAfterValue": "1000003",
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"UMask": "0x1",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Counts all microcode FP assists.",
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"EventCode": "0xc1",
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"EventName": "ASSISTS.FP",
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"PublicDescription": "Counts all microcode Floating Point assists.",
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"SampleAfterValue": "100003",
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"UMask": "0x2",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "ASSISTS.SSE_AVX_MIX",
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"EventCode": "0xc1",
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"EventName": "ASSISTS.SSE_AVX_MIX",
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"SampleAfterValue": "1000003",
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"UMask": "0x10",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "FP_ARITH_DISPATCHED.PORT_0 [This event is alias to FP_ARITH_DISPATCHED.V0]",
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"EventCode": "0xb3",
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"EventName": "FP_ARITH_DISPATCHED.PORT_0",
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"SampleAfterValue": "2000003",
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"UMask": "0x1",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "FP_ARITH_DISPATCHED.PORT_1 [This event is alias to FP_ARITH_DISPATCHED.V1]",
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"EventCode": "0xb3",
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"EventName": "FP_ARITH_DISPATCHED.PORT_1",
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"SampleAfterValue": "2000003",
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"UMask": "0x2",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "FP_ARITH_DISPATCHED.PORT_5 [This event is alias to FP_ARITH_DISPATCHED.V2]",
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"EventCode": "0xb3",
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"EventName": "FP_ARITH_DISPATCHED.PORT_5",
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"SampleAfterValue": "2000003",
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"UMask": "0x4",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "FP_ARITH_DISPATCHED.V0 [This event is alias to FP_ARITH_DISPATCHED.PORT_0]",
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"EventCode": "0xb3",
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"EventName": "FP_ARITH_DISPATCHED.V0",
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"SampleAfterValue": "2000003",
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"UMask": "0x1",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "FP_ARITH_DISPATCHED.V1 [This event is alias to FP_ARITH_DISPATCHED.PORT_1]",
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"EventCode": "0xb3",
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"EventName": "FP_ARITH_DISPATCHED.V1",
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"SampleAfterValue": "2000003",
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"UMask": "0x2",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "FP_ARITH_DISPATCHED.V2 [This event is alias to FP_ARITH_DISPATCHED.PORT_5]",
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"EventCode": "0xb3",
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"EventName": "FP_ARITH_DISPATCHED.V2",
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"SampleAfterValue": "2000003",
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"UMask": "0x4",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
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"EventCode": "0xc7",
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"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
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"PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
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"SampleAfterValue": "100003",
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"UMask": "0x4",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
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"EventCode": "0xc7",
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"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
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"PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
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"SampleAfterValue": "100003",
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"UMask": "0x8",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
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"EventCode": "0xc7",
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"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
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"PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
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"SampleAfterValue": "100003",
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"UMask": "0x10",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
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"EventCode": "0xc7",
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"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
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"PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
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"SampleAfterValue": "100003",
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"UMask": "0x20",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.",
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"EventCode": "0xc7",
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"EventName": "FP_ARITH_INST_RETIRED.4_FLOPS",
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"PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
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"SampleAfterValue": "100003",
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"UMask": "0x18",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
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"EventCode": "0xc7",
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"EventName": "FP_ARITH_INST_RETIRED.SCALAR",
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"PublicDescription": "Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
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"SampleAfterValue": "1000003",
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"UMask": "0x3",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
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"EventCode": "0xc7",
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"EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
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"PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
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"SampleAfterValue": "100003",
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"UMask": "0x1",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
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"EventCode": "0xc7",
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"EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
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"PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
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"SampleAfterValue": "100003",
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"UMask": "0x2",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Number of any Vector retired FP arithmetic instructions",
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"EventCode": "0xc7",
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"EventName": "FP_ARITH_INST_RETIRED.VECTOR",
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"PublicDescription": "Number of any Vector retired FP arithmetic instructions. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
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"SampleAfterValue": "1000003",
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"UMask": "0xfc",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Counts the number of floating point operations retired that required microcode assist.",
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"EventCode": "0xc3",
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"EventName": "MACHINE_CLEARS.FP_ASSIST",
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"PublicDescription": "Counts the number of floating point operations retired that required microcode assist, which is not a reflection of the number of FP operations, instructions or uops.",
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"SampleAfterValue": "20003",
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"UMask": "0x4",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of floating point divide uops retired (x87 and SSE, including x87 sqrt).",
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"EventCode": "0xc2",
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"EventName": "UOPS_RETIRED.FPDIV",
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"PEBS": "1",
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"SampleAfterValue": "2000003",
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"UMask": "0x8",
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"Unit": "cpu_atom"
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}
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]
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