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![Linus Walleij](/assets/img/avatar_default.png)
This replace all instances in the i2c busses tree of res->end - res->start + 1 with the handy macro resource_size(res) from ioport.h (coming in from platform_device.h). This was created with a simple sed -i -e 's/\([a-z]*\)->end *- *[a-z]*->start *+ *1/resource_size(\1)/g' Then manually replacing the PXA redefiniton of the same kind of macro manually. Recompiled some ARM defconfigs I could find to make a rough test so it shouldn't break anything, though I couldn't see exactly which configs you need for all the drivers. Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
497 lines
10 KiB
C
497 lines
10 KiB
C
/*
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* i2c-au1550.c: SMBus (i2c) adapter for Alchemy PSC interface
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* Copyright (C) 2004 Embedded Edge, LLC <dan@embeddededge.com>
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*
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* 2.6 port by Matt Porter <mporter@kernel.crashing.org>
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*
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* The documentation describes this as an SMBus controller, but it doesn't
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* understand any of the SMBus protocol in hardware. It's really an I2C
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* controller that could emulate most of the SMBus in software.
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*
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* This is just a skeleton adapter to use with the Au1550 PSC
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* algorithm. It was developed for the Pb1550, but will work with
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* any Au1550 board that has a similar PSC configuration.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#include <linux/delay.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/i2c.h>
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#include <linux/slab.h>
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#include <asm/mach-au1x00/au1xxx.h>
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#include <asm/mach-au1x00/au1xxx_psc.h>
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struct i2c_au1550_data {
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u32 psc_base;
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int xfer_timeout;
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int ack_timeout;
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struct i2c_adapter adap;
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struct resource *ioarea;
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};
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static int
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wait_xfer_done(struct i2c_au1550_data *adap)
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{
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u32 stat;
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int i;
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volatile psc_smb_t *sp;
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sp = (volatile psc_smb_t *)(adap->psc_base);
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/* Wait for Tx Buffer Empty
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*/
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for (i = 0; i < adap->xfer_timeout; i++) {
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stat = sp->psc_smbstat;
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au_sync();
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if ((stat & PSC_SMBSTAT_TE) != 0)
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return 0;
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udelay(1);
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}
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return -ETIMEDOUT;
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}
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static int
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wait_ack(struct i2c_au1550_data *adap)
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{
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u32 stat;
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volatile psc_smb_t *sp;
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if (wait_xfer_done(adap))
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return -ETIMEDOUT;
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sp = (volatile psc_smb_t *)(adap->psc_base);
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stat = sp->psc_smbevnt;
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au_sync();
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if ((stat & (PSC_SMBEVNT_DN | PSC_SMBEVNT_AN | PSC_SMBEVNT_AL)) != 0)
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return -ETIMEDOUT;
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return 0;
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}
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static int
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wait_master_done(struct i2c_au1550_data *adap)
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{
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u32 stat;
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int i;
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volatile psc_smb_t *sp;
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sp = (volatile psc_smb_t *)(adap->psc_base);
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/* Wait for Master Done.
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*/
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for (i = 0; i < adap->xfer_timeout; i++) {
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stat = sp->psc_smbevnt;
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au_sync();
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if ((stat & PSC_SMBEVNT_MD) != 0)
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return 0;
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udelay(1);
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}
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return -ETIMEDOUT;
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}
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static int
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do_address(struct i2c_au1550_data *adap, unsigned int addr, int rd, int q)
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{
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volatile psc_smb_t *sp;
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u32 stat;
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sp = (volatile psc_smb_t *)(adap->psc_base);
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/* Reset the FIFOs, clear events.
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*/
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stat = sp->psc_smbstat;
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sp->psc_smbevnt = PSC_SMBEVNT_ALLCLR;
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au_sync();
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if (!(stat & PSC_SMBSTAT_TE) || !(stat & PSC_SMBSTAT_RE)) {
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sp->psc_smbpcr = PSC_SMBPCR_DC;
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au_sync();
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do {
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stat = sp->psc_smbpcr;
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au_sync();
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} while ((stat & PSC_SMBPCR_DC) != 0);
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udelay(50);
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}
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/* Write out the i2c chip address and specify operation
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*/
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addr <<= 1;
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if (rd)
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addr |= 1;
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/* zero-byte xfers stop immediately */
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if (q)
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addr |= PSC_SMBTXRX_STP;
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/* Put byte into fifo, start up master.
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*/
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sp->psc_smbtxrx = addr;
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au_sync();
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sp->psc_smbpcr = PSC_SMBPCR_MS;
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au_sync();
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if (wait_ack(adap))
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return -EIO;
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return (q) ? wait_master_done(adap) : 0;
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}
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static u32
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wait_for_rx_byte(struct i2c_au1550_data *adap, u32 *ret_data)
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{
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int j;
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u32 data, stat;
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volatile psc_smb_t *sp;
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if (wait_xfer_done(adap))
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return -EIO;
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sp = (volatile psc_smb_t *)(adap->psc_base);
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j = adap->xfer_timeout * 100;
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do {
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j--;
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if (j <= 0)
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return -EIO;
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stat = sp->psc_smbstat;
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au_sync();
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if ((stat & PSC_SMBSTAT_RE) == 0)
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j = 0;
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else
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udelay(1);
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} while (j > 0);
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data = sp->psc_smbtxrx;
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au_sync();
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*ret_data = data;
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return 0;
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}
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static int
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i2c_read(struct i2c_au1550_data *adap, unsigned char *buf,
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unsigned int len)
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{
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int i;
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u32 data;
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volatile psc_smb_t *sp;
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if (len == 0)
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return 0;
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/* A read is performed by stuffing the transmit fifo with
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* zero bytes for timing, waiting for bytes to appear in the
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* receive fifo, then reading the bytes.
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*/
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sp = (volatile psc_smb_t *)(adap->psc_base);
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i = 0;
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while (i < (len-1)) {
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sp->psc_smbtxrx = 0;
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au_sync();
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if (wait_for_rx_byte(adap, &data))
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return -EIO;
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buf[i] = data;
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i++;
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}
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/* The last byte has to indicate transfer done.
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*/
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sp->psc_smbtxrx = PSC_SMBTXRX_STP;
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au_sync();
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if (wait_master_done(adap))
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return -EIO;
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data = sp->psc_smbtxrx;
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au_sync();
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buf[i] = data;
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return 0;
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}
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static int
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i2c_write(struct i2c_au1550_data *adap, unsigned char *buf,
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unsigned int len)
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{
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int i;
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u32 data;
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volatile psc_smb_t *sp;
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if (len == 0)
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return 0;
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sp = (volatile psc_smb_t *)(adap->psc_base);
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i = 0;
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while (i < (len-1)) {
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data = buf[i];
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sp->psc_smbtxrx = data;
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au_sync();
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if (wait_ack(adap))
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return -EIO;
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i++;
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}
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/* The last byte has to indicate transfer done.
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*/
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data = buf[i];
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data |= PSC_SMBTXRX_STP;
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sp->psc_smbtxrx = data;
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au_sync();
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if (wait_master_done(adap))
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return -EIO;
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return 0;
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}
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static int
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au1550_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, int num)
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{
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struct i2c_au1550_data *adap = i2c_adap->algo_data;
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volatile psc_smb_t *sp = (volatile psc_smb_t *)adap->psc_base;
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struct i2c_msg *p;
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int i, err = 0;
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sp->psc_ctrl = PSC_CTRL_ENABLE;
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au_sync();
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for (i = 0; !err && i < num; i++) {
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p = &msgs[i];
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err = do_address(adap, p->addr, p->flags & I2C_M_RD,
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(p->len == 0));
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if (err || !p->len)
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continue;
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if (p->flags & I2C_M_RD)
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err = i2c_read(adap, p->buf, p->len);
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else
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err = i2c_write(adap, p->buf, p->len);
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}
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/* Return the number of messages processed, or the error code.
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*/
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if (err == 0)
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err = num;
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sp->psc_ctrl = PSC_CTRL_SUSPEND;
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au_sync();
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return err;
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}
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static u32
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au1550_func(struct i2c_adapter *adap)
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{
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return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
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}
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static const struct i2c_algorithm au1550_algo = {
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.master_xfer = au1550_xfer,
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.functionality = au1550_func,
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};
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static void i2c_au1550_setup(struct i2c_au1550_data *priv)
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{
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volatile psc_smb_t *sp = (volatile psc_smb_t *)priv->psc_base;
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u32 stat;
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sp->psc_ctrl = PSC_CTRL_DISABLE;
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au_sync();
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sp->psc_sel = PSC_SEL_PS_SMBUSMODE;
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sp->psc_smbcfg = 0;
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au_sync();
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sp->psc_ctrl = PSC_CTRL_ENABLE;
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au_sync();
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do {
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stat = sp->psc_smbstat;
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au_sync();
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} while ((stat & PSC_SMBSTAT_SR) == 0);
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sp->psc_smbcfg = (PSC_SMBCFG_RT_FIFO8 | PSC_SMBCFG_TT_FIFO8 |
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PSC_SMBCFG_DD_DISABLE);
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/* Divide by 8 to get a 6.25 MHz clock. The later protocol
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* timings are based on this clock.
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*/
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sp->psc_smbcfg |= PSC_SMBCFG_SET_DIV(PSC_SMBCFG_DIV8);
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sp->psc_smbmsk = PSC_SMBMSK_ALLMASK;
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au_sync();
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/* Set the protocol timer values. See Table 71 in the
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* Au1550 Data Book for standard timing values.
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*/
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sp->psc_smbtmr = PSC_SMBTMR_SET_TH(0) | PSC_SMBTMR_SET_PS(15) | \
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PSC_SMBTMR_SET_PU(15) | PSC_SMBTMR_SET_SH(15) | \
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PSC_SMBTMR_SET_SU(15) | PSC_SMBTMR_SET_CL(15) | \
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PSC_SMBTMR_SET_CH(15);
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au_sync();
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sp->psc_smbcfg |= PSC_SMBCFG_DE_ENABLE;
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do {
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stat = sp->psc_smbstat;
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au_sync();
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} while ((stat & PSC_SMBSTAT_SR) == 0);
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sp->psc_ctrl = PSC_CTRL_SUSPEND;
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au_sync();
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}
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static void i2c_au1550_disable(struct i2c_au1550_data *priv)
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{
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volatile psc_smb_t *sp = (volatile psc_smb_t *)priv->psc_base;
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sp->psc_smbcfg = 0;
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sp->psc_ctrl = PSC_CTRL_DISABLE;
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au_sync();
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}
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/*
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* registering functions to load algorithms at runtime
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* Prior to calling us, the 50MHz clock frequency and routing
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* must have been set up for the PSC indicated by the adapter.
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*/
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static int __devinit
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i2c_au1550_probe(struct platform_device *pdev)
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{
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struct i2c_au1550_data *priv;
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struct resource *r;
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int ret;
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!r) {
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ret = -ENODEV;
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goto out;
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}
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priv = kzalloc(sizeof(struct i2c_au1550_data), GFP_KERNEL);
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if (!priv) {
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ret = -ENOMEM;
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goto out;
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}
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priv->ioarea = request_mem_region(r->start, resource_size(r),
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pdev->name);
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if (!priv->ioarea) {
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ret = -EBUSY;
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goto out_mem;
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}
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priv->psc_base = CKSEG1ADDR(r->start);
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priv->xfer_timeout = 200;
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priv->ack_timeout = 200;
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priv->adap.nr = pdev->id;
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priv->adap.algo = &au1550_algo;
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priv->adap.algo_data = priv;
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priv->adap.dev.parent = &pdev->dev;
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strlcpy(priv->adap.name, "Au1xxx PSC I2C", sizeof(priv->adap.name));
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/* Now, set up the PSC for SMBus PIO mode.
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*/
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i2c_au1550_setup(priv);
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ret = i2c_add_numbered_adapter(&priv->adap);
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if (ret == 0) {
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platform_set_drvdata(pdev, priv);
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return 0;
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}
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i2c_au1550_disable(priv);
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release_resource(priv->ioarea);
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kfree(priv->ioarea);
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out_mem:
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kfree(priv);
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out:
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return ret;
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}
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static int __devexit
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i2c_au1550_remove(struct platform_device *pdev)
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{
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struct i2c_au1550_data *priv = platform_get_drvdata(pdev);
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platform_set_drvdata(pdev, NULL);
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i2c_del_adapter(&priv->adap);
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i2c_au1550_disable(priv);
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release_resource(priv->ioarea);
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kfree(priv->ioarea);
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kfree(priv);
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return 0;
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}
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#ifdef CONFIG_PM
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static int
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i2c_au1550_suspend(struct platform_device *pdev, pm_message_t state)
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{
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struct i2c_au1550_data *priv = platform_get_drvdata(pdev);
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i2c_au1550_disable(priv);
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return 0;
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}
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static int
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i2c_au1550_resume(struct platform_device *pdev)
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{
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struct i2c_au1550_data *priv = platform_get_drvdata(pdev);
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i2c_au1550_setup(priv);
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return 0;
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}
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#else
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#define i2c_au1550_suspend NULL
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#define i2c_au1550_resume NULL
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#endif
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static struct platform_driver au1xpsc_smbus_driver = {
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.driver = {
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.name = "au1xpsc_smbus",
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.owner = THIS_MODULE,
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},
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.probe = i2c_au1550_probe,
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.remove = __devexit_p(i2c_au1550_remove),
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.suspend = i2c_au1550_suspend,
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.resume = i2c_au1550_resume,
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};
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static int __init
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i2c_au1550_init(void)
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{
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return platform_driver_register(&au1xpsc_smbus_driver);
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}
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static void __exit
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i2c_au1550_exit(void)
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{
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platform_driver_unregister(&au1xpsc_smbus_driver);
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}
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MODULE_AUTHOR("Dan Malek, Embedded Edge, LLC.");
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MODULE_DESCRIPTION("SMBus adapter Alchemy pb1550");
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MODULE_LICENSE("GPL");
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MODULE_ALIAS("platform:au1xpsc_smbus");
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module_init (i2c_au1550_init);
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module_exit (i2c_au1550_exit);
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