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1d5013f1b6
Rates declared in PLL rate tables should match exactly rates calculated from PLL coefficients. To avoid possible mistakes we can use compile time validation. The patch introduces such validators and expands all initializers with additional input frequency parameter, required to validate rates. Since S3C24xx PLLs requires different validators two new macros have been introduced to deal with it. Also, since PLLs 4502 and 4508 have different formulas PLL_45XX_RATE has been replaced with PLL_4508_RATE. As the patch adds only compile time validators it should not have impact on compiled code. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Tomasz Figa <tomasz.figa@gmail.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> |
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| .. | ||
| clk-cpu.c | ||
| clk-cpu.h | ||
| clk-exynos-audss.c | ||
| clk-exynos-clkout.c | ||
| clk-exynos4.c | ||
| clk-exynos7.c | ||
| clk-exynos3250.c | ||
| clk-exynos4412-isp.c | ||
| clk-exynos5250.c | ||
| clk-exynos5260.c | ||
| clk-exynos5260.h | ||
| clk-exynos5410.c | ||
| clk-exynos5420.c | ||
| clk-exynos5433.c | ||
| clk-exynos5440.c | ||
| clk-pll.c | ||
| clk-pll.h | ||
| clk-s3c64xx.c | ||
| clk-s3c2410-dclk.c | ||
| clk-s3c2410.c | ||
| clk-s3c2412.c | ||
| clk-s3c2443.c | ||
| clk-s5pv210-audss.c | ||
| clk-s5pv210.c | ||
| clk.c | ||
| clk.h | ||
| Kconfig | ||
| Makefile | ||