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![Martin Povišer](/assets/img/avatar_default.png)
Signed-off-by: Martin Povišer <povik+lin@cutebit.org> Link: https://lore.kernel.org/r/20220312135722.20770-1-povik+lin@cutebit.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
334 lines
8.6 KiB
C
334 lines
8.6 KiB
C
// SPDX-License-Identifier: GPL-2.0-only OR MIT
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/*
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* Driver for an SoC block (Numerically Controlled Oscillator)
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* found on t8103 (M1) and other Apple chips
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*
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* Copyright (C) The Asahi Linux Contributors
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*/
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#include <linux/bits.h>
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#include <linux/bitfield.h>
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/math64.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#define NCO_CHANNEL_STRIDE 0x4000
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#define NCO_CHANNEL_REGSIZE 20
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#define REG_CTRL 0
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#define CTRL_ENABLE BIT(31)
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#define REG_DIV 4
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#define DIV_FINE GENMASK(1, 0)
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#define DIV_COARSE GENMASK(12, 2)
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#define REG_INC1 8
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#define REG_INC2 12
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#define REG_ACCINIT 16
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/*
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* Theory of operation (postulated)
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*
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* The REG_DIV register indirectly expresses a base integer divisor, roughly
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* corresponding to twice the desired ratio of input to output clock. This
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* base divisor is adjusted on a cycle-by-cycle basis based on the state of a
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* 32-bit phase accumulator to achieve a desired precise clock ratio over the
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* long term.
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*
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* Specifically an output clock cycle is produced after (REG_DIV divisor)/2
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* or (REG_DIV divisor + 1)/2 input cycles, the latter taking effect when top
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* bit of the 32-bit accumulator is set. The accumulator is incremented each
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* produced output cycle, by the value from either REG_INC1 or REG_INC2, which
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* of the two is selected depending again on the accumulator's current top bit.
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*
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* Because the NCO hardware implements counting of input clock cycles in part
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* in a Galois linear-feedback shift register, the higher bits of divisor
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* are programmed into REG_DIV by picking an appropriate LFSR state. See
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* applnco_compute_tables/applnco_div_translate for details on this.
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*/
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#define LFSR_POLY 0xa01
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#define LFSR_INIT 0x7ff
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#define LFSR_LEN 11
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#define LFSR_PERIOD ((1 << LFSR_LEN) - 1)
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#define LFSR_TBLSIZE (1 << LFSR_LEN)
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/* The minimal attainable coarse divisor (first value in table) */
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#define COARSE_DIV_OFFSET 2
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struct applnco_tables {
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u16 fwd[LFSR_TBLSIZE];
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u16 inv[LFSR_TBLSIZE];
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};
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struct applnco_channel {
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void __iomem *base;
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struct applnco_tables *tbl;
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struct clk_hw hw;
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spinlock_t lock;
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};
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#define to_applnco_channel(_hw) container_of(_hw, struct applnco_channel, hw)
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static void applnco_enable_nolock(struct clk_hw *hw)
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{
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struct applnco_channel *chan = to_applnco_channel(hw);
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u32 val;
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val = readl_relaxed(chan->base + REG_CTRL);
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writel_relaxed(val | CTRL_ENABLE, chan->base + REG_CTRL);
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}
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static void applnco_disable_nolock(struct clk_hw *hw)
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{
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struct applnco_channel *chan = to_applnco_channel(hw);
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u32 val;
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val = readl_relaxed(chan->base + REG_CTRL);
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writel_relaxed(val & ~CTRL_ENABLE, chan->base + REG_CTRL);
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}
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static int applnco_is_enabled(struct clk_hw *hw)
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{
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struct applnco_channel *chan = to_applnco_channel(hw);
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return (readl_relaxed(chan->base + REG_CTRL) & CTRL_ENABLE) != 0;
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}
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static void applnco_compute_tables(struct applnco_tables *tbl)
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{
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int i;
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u32 state = LFSR_INIT;
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/*
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* Go through the states of a Galois LFSR and build
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* a coarse divisor translation table.
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*/
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for (i = LFSR_PERIOD; i > 0; i--) {
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if (state & 1)
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state = (state >> 1) ^ (LFSR_POLY >> 1);
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else
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state = (state >> 1);
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tbl->fwd[i] = state;
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tbl->inv[state] = i;
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}
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/* Zero value is special-cased */
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tbl->fwd[0] = 0;
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tbl->inv[0] = 0;
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}
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static bool applnco_div_out_of_range(unsigned int div)
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{
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unsigned int coarse = div / 4;
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return coarse < COARSE_DIV_OFFSET ||
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coarse >= COARSE_DIV_OFFSET + LFSR_TBLSIZE;
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}
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static u32 applnco_div_translate(struct applnco_tables *tbl, unsigned int div)
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{
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unsigned int coarse = div / 4;
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if (WARN_ON(applnco_div_out_of_range(div)))
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return 0;
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return FIELD_PREP(DIV_COARSE, tbl->fwd[coarse - COARSE_DIV_OFFSET]) |
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FIELD_PREP(DIV_FINE, div % 4);
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}
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static unsigned int applnco_div_translate_inv(struct applnco_tables *tbl, u32 regval)
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{
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unsigned int coarse, fine;
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coarse = tbl->inv[FIELD_GET(DIV_COARSE, regval)] + COARSE_DIV_OFFSET;
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fine = FIELD_GET(DIV_FINE, regval);
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return coarse * 4 + fine;
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}
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static int applnco_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct applnco_channel *chan = to_applnco_channel(hw);
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unsigned long flags;
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u32 div, inc1, inc2;
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bool was_enabled;
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div = 2 * parent_rate / rate;
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inc1 = 2 * parent_rate - div * rate;
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inc2 = inc1 - rate;
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if (applnco_div_out_of_range(div))
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return -EINVAL;
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div = applnco_div_translate(chan->tbl, div);
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spin_lock_irqsave(&chan->lock, flags);
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was_enabled = applnco_is_enabled(hw);
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applnco_disable_nolock(hw);
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writel_relaxed(div, chan->base + REG_DIV);
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writel_relaxed(inc1, chan->base + REG_INC1);
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writel_relaxed(inc2, chan->base + REG_INC2);
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/* Presumably a neutral initial value for accumulator */
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writel_relaxed(1 << 31, chan->base + REG_ACCINIT);
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if (was_enabled)
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applnco_enable_nolock(hw);
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spin_unlock_irqrestore(&chan->lock, flags);
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return 0;
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}
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static unsigned long applnco_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct applnco_channel *chan = to_applnco_channel(hw);
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u32 div, inc1, inc2, incbase;
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div = applnco_div_translate_inv(chan->tbl,
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readl_relaxed(chan->base + REG_DIV));
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inc1 = readl_relaxed(chan->base + REG_INC1);
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inc2 = readl_relaxed(chan->base + REG_INC2);
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/*
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* We don't support wraparound of accumulator
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* nor the edge case of both increments being zero
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*/
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if (inc1 >= (1 << 31) || inc2 < (1 << 31) || (inc1 == 0 && inc2 == 0))
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return 0;
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/* Scale both sides of division by incbase to maintain precision */
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incbase = inc1 - inc2;
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return div64_u64(((u64) parent_rate) * 2 * incbase,
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((u64) div) * incbase + inc1);
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}
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static long applnco_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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unsigned long lo = *parent_rate / (COARSE_DIV_OFFSET + LFSR_TBLSIZE) + 1;
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unsigned long hi = *parent_rate / COARSE_DIV_OFFSET;
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return clamp(rate, lo, hi);
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}
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static int applnco_enable(struct clk_hw *hw)
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{
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struct applnco_channel *chan = to_applnco_channel(hw);
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unsigned long flags;
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spin_lock_irqsave(&chan->lock, flags);
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applnco_enable_nolock(hw);
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spin_unlock_irqrestore(&chan->lock, flags);
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return 0;
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}
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static void applnco_disable(struct clk_hw *hw)
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{
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struct applnco_channel *chan = to_applnco_channel(hw);
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unsigned long flags;
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spin_lock_irqsave(&chan->lock, flags);
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applnco_disable_nolock(hw);
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spin_unlock_irqrestore(&chan->lock, flags);
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}
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static const struct clk_ops applnco_ops = {
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.set_rate = applnco_set_rate,
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.recalc_rate = applnco_recalc_rate,
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.round_rate = applnco_round_rate,
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.enable = applnco_enable,
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.disable = applnco_disable,
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.is_enabled = applnco_is_enabled,
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};
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static int applnco_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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struct clk_parent_data pdata = { .index = 0 };
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struct clk_init_data init;
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struct clk_hw_onecell_data *onecell_data;
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void __iomem *base;
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struct resource *res;
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struct applnco_tables *tbl;
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unsigned int nchannels;
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int ret, i;
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base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
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if (IS_ERR(base))
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return PTR_ERR(base);
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if (resource_size(res) < NCO_CHANNEL_REGSIZE)
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return -EINVAL;
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nchannels = (resource_size(res) - NCO_CHANNEL_REGSIZE)
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/ NCO_CHANNEL_STRIDE + 1;
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onecell_data = devm_kzalloc(&pdev->dev, struct_size(onecell_data, hws,
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nchannels), GFP_KERNEL);
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if (!onecell_data)
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return -ENOMEM;
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onecell_data->num = nchannels;
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tbl = devm_kzalloc(&pdev->dev, sizeof(*tbl), GFP_KERNEL);
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if (!tbl)
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return -ENOMEM;
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applnco_compute_tables(tbl);
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for (i = 0; i < nchannels; i++) {
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struct applnco_channel *chan;
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chan = devm_kzalloc(&pdev->dev, sizeof(*chan), GFP_KERNEL);
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if (!chan)
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return -ENOMEM;
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chan->base = base + NCO_CHANNEL_STRIDE * i;
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chan->tbl = tbl;
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spin_lock_init(&chan->lock);
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memset(&init, 0, sizeof(init));
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init.name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
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"%s-%d", np->name, i);
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init.ops = &applnco_ops;
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init.parent_data = &pdata;
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init.num_parents = 1;
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init.flags = 0;
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chan->hw.init = &init;
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ret = devm_clk_hw_register(&pdev->dev, &chan->hw);
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if (ret)
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return ret;
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onecell_data->hws[i] = &chan->hw;
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}
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return devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get,
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onecell_data);
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}
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static const struct of_device_id applnco_ids[] = {
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{ .compatible = "apple,nco" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, applnco_ids);
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static struct platform_driver applnco_driver = {
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.driver = {
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.name = "apple-nco",
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.of_match_table = applnco_ids,
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},
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.probe = applnco_probe,
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};
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module_platform_driver(applnco_driver);
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MODULE_AUTHOR("Martin Povišer <povik+lin@cutebit.org>");
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MODULE_DESCRIPTION("Clock driver for NCO blocks on Apple SoCs");
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MODULE_LICENSE("GPL");
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