mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-12 21:57:43 +00:00
8da312d657
The Frequency Hopping Controller (FHCTL) seems to have different versions, as it has a slightly different register layout on some older SoCs like MT6795, MT8173, MT8183 (and others). This driver is indeed compatible with at least some of those older IP revisions, so all we need to do is to add a way to select the right register layout at registration time. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230206100105.861720-2-angelogioacchino.delregno@collabora.com Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
33 lines
656 B
C
33 lines
656 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
|
|
/*
|
|
* Copyright (c) 2022 MediaTek Inc.
|
|
* Author: Edward-JW Yang <edward-jw.yang@mediatek.com>
|
|
*/
|
|
|
|
#ifndef __CLK_FHCTL_H
|
|
#define __CLK_FHCTL_H
|
|
|
|
#include "clk-pllfh.h"
|
|
|
|
enum fhctl_variant {
|
|
FHCTL_PLLFH_V1,
|
|
FHCTL_PLLFH_V2,
|
|
};
|
|
|
|
struct fhctl_offset {
|
|
u32 offset_hp_en;
|
|
u32 offset_clk_con;
|
|
u32 offset_rst_con;
|
|
u32 offset_slope0;
|
|
u32 offset_slope1;
|
|
u32 offset_cfg;
|
|
u32 offset_updnlmt;
|
|
u32 offset_dds;
|
|
u32 offset_dvfs;
|
|
u32 offset_mon;
|
|
};
|
|
const struct fhctl_offset *fhctl_get_offset_table(enum fhctl_variant v);
|
|
const struct fh_operation *fhctl_get_ops(void);
|
|
void fhctl_hw_init(struct mtk_fh *fh);
|
|
|
|
#endif
|