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5b5b5806f2
IPQ95xx SoCs have different OPPs available for the CPU based on the SoC variant. This can be determined from an eFuse register present in the silicon. Added support for ipq95xx on nvmem driver which helps to determine OPPs at runtime based on the eFuse register which has the CPU frequency limits. opp-supported-hw dt binding can be used to indicate the available OPPs for each limit. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Praveenkumar I <ipkumar@codeaurora.org> Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> [ Viresh: Fixed subject ] Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
235 lines
6.6 KiB
C
235 lines
6.6 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2016 Linaro.
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* Viresh Kumar <viresh.kumar@linaro.org>
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*/
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#include <linux/err.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include "cpufreq-dt.h"
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/*
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* Machines for which the cpufreq device is *always* created, mostly used for
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* platforms using "operating-points" (V1) property.
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*/
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static const struct of_device_id allowlist[] __initconst = {
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{ .compatible = "allwinner,sun4i-a10", },
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{ .compatible = "allwinner,sun5i-a10s", },
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{ .compatible = "allwinner,sun5i-a13", },
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{ .compatible = "allwinner,sun5i-r8", },
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{ .compatible = "allwinner,sun6i-a31", },
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{ .compatible = "allwinner,sun6i-a31s", },
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{ .compatible = "allwinner,sun7i-a20", },
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{ .compatible = "allwinner,sun8i-a23", },
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{ .compatible = "allwinner,sun8i-a83t", },
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{ .compatible = "allwinner,sun8i-h3", },
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{ .compatible = "apm,xgene-shadowcat", },
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{ .compatible = "arm,integrator-ap", },
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{ .compatible = "arm,integrator-cp", },
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{ .compatible = "hisilicon,hi3660", },
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{ .compatible = "fsl,imx27", },
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{ .compatible = "fsl,imx51", },
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{ .compatible = "fsl,imx53", },
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{ .compatible = "marvell,berlin", },
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{ .compatible = "marvell,pxa250", },
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{ .compatible = "marvell,pxa270", },
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{ .compatible = "samsung,exynos3250", },
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{ .compatible = "samsung,exynos4210", },
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{ .compatible = "samsung,exynos5250", },
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#ifndef CONFIG_BL_SWITCHER
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{ .compatible = "samsung,exynos5800", },
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#endif
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{ .compatible = "renesas,emev2", },
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{ .compatible = "renesas,r7s72100", },
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{ .compatible = "renesas,r8a73a4", },
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{ .compatible = "renesas,r8a7740", },
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{ .compatible = "renesas,r8a7742", },
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{ .compatible = "renesas,r8a7743", },
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{ .compatible = "renesas,r8a7744", },
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{ .compatible = "renesas,r8a7745", },
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{ .compatible = "renesas,r8a7778", },
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{ .compatible = "renesas,r8a7779", },
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{ .compatible = "renesas,r8a7790", },
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{ .compatible = "renesas,r8a7791", },
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{ .compatible = "renesas,r8a7792", },
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{ .compatible = "renesas,r8a7793", },
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{ .compatible = "renesas,r8a7794", },
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{ .compatible = "renesas,sh73a0", },
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{ .compatible = "rockchip,rk2928", },
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{ .compatible = "rockchip,rk3036", },
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{ .compatible = "rockchip,rk3066a", },
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{ .compatible = "rockchip,rk3066b", },
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{ .compatible = "rockchip,rk3188", },
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{ .compatible = "rockchip,rk3228", },
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{ .compatible = "rockchip,rk3288", },
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{ .compatible = "rockchip,rk3328", },
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{ .compatible = "rockchip,rk3366", },
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{ .compatible = "rockchip,rk3368", },
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{ .compatible = "rockchip,rk3399",
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.data = &(struct cpufreq_dt_platform_data)
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{ .have_governor_per_policy = true, },
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},
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{ .compatible = "st-ericsson,u8500", },
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{ .compatible = "st-ericsson,u8540", },
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{ .compatible = "st-ericsson,u9500", },
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{ .compatible = "st-ericsson,u9540", },
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{ .compatible = "starfive,jh7110", },
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{ .compatible = "ti,omap2", },
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{ .compatible = "ti,omap4", },
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{ .compatible = "ti,omap5", },
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{ .compatible = "xlnx,zynq-7000", },
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{ .compatible = "xlnx,zynqmp", },
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{ }
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};
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/*
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* Machines for which the cpufreq device is *not* created, mostly used for
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* platforms using "operating-points-v2" property.
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*/
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static const struct of_device_id blocklist[] __initconst = {
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{ .compatible = "allwinner,sun50i-h6", },
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{ .compatible = "apple,arm-platform", },
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{ .compatible = "arm,vexpress", },
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{ .compatible = "calxeda,highbank", },
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{ .compatible = "calxeda,ecx-2000", },
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{ .compatible = "fsl,imx7ulp", },
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{ .compatible = "fsl,imx7d", },
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{ .compatible = "fsl,imx7s", },
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{ .compatible = "fsl,imx8mq", },
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{ .compatible = "fsl,imx8mm", },
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{ .compatible = "fsl,imx8mn", },
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{ .compatible = "fsl,imx8mp", },
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{ .compatible = "marvell,armadaxp", },
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{ .compatible = "mediatek,mt2701", },
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{ .compatible = "mediatek,mt2712", },
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{ .compatible = "mediatek,mt7622", },
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{ .compatible = "mediatek,mt7623", },
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{ .compatible = "mediatek,mt8167", },
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{ .compatible = "mediatek,mt817x", },
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{ .compatible = "mediatek,mt8173", },
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{ .compatible = "mediatek,mt8176", },
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{ .compatible = "mediatek,mt8183", },
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{ .compatible = "mediatek,mt8186", },
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{ .compatible = "mediatek,mt8365", },
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{ .compatible = "mediatek,mt8516", },
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{ .compatible = "nvidia,tegra20", },
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{ .compatible = "nvidia,tegra30", },
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{ .compatible = "nvidia,tegra124", },
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{ .compatible = "nvidia,tegra210", },
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{ .compatible = "nvidia,tegra234", },
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{ .compatible = "qcom,apq8096", },
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{ .compatible = "qcom,msm8909", },
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{ .compatible = "qcom,msm8996", },
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{ .compatible = "qcom,msm8998", },
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{ .compatible = "qcom,qcm2290", },
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{ .compatible = "qcom,qcm6490", },
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{ .compatible = "qcom,qcs404", },
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{ .compatible = "qcom,qdu1000", },
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{ .compatible = "qcom,sa8155p" },
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{ .compatible = "qcom,sa8540p" },
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{ .compatible = "qcom,sa8775p" },
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{ .compatible = "qcom,sc7180", },
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{ .compatible = "qcom,sc7280", },
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{ .compatible = "qcom,sc8180x", },
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{ .compatible = "qcom,sc8280xp", },
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{ .compatible = "qcom,sdm845", },
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{ .compatible = "qcom,sdx75", },
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{ .compatible = "qcom,sm6115", },
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{ .compatible = "qcom,sm6350", },
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{ .compatible = "qcom,sm6375", },
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{ .compatible = "qcom,sm7225", },
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{ .compatible = "qcom,sm8150", },
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{ .compatible = "qcom,sm8250", },
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{ .compatible = "qcom,sm8350", },
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{ .compatible = "qcom,sm8450", },
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{ .compatible = "qcom,sm8550", },
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{ .compatible = "st,stih407", },
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{ .compatible = "st,stih410", },
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{ .compatible = "st,stih418", },
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{ .compatible = "ti,am33xx", },
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{ .compatible = "ti,am43", },
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{ .compatible = "ti,dra7", },
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{ .compatible = "ti,omap3", },
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{ .compatible = "ti,am625", },
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{ .compatible = "ti,am62a7", },
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{ .compatible = "ti,am62p5", },
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{ .compatible = "qcom,ipq5332", },
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{ .compatible = "qcom,ipq6018", },
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{ .compatible = "qcom,ipq8064", },
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{ .compatible = "qcom,ipq8074", },
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{ .compatible = "qcom,ipq9574", },
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{ .compatible = "qcom,apq8064", },
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{ .compatible = "qcom,msm8974", },
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{ .compatible = "qcom,msm8960", },
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{ }
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};
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static bool __init cpu0_node_has_opp_v2_prop(void)
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{
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struct device_node *np = of_cpu_device_node_get(0);
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bool ret = false;
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if (of_property_present(np, "operating-points-v2"))
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ret = true;
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of_node_put(np);
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return ret;
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}
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static int __init cpufreq_dt_platdev_init(void)
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{
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struct device_node *np = of_find_node_by_path("/");
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const struct of_device_id *match;
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const void *data = NULL;
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if (!np)
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return -ENODEV;
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match = of_match_node(allowlist, np);
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if (match) {
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data = match->data;
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goto create_pdev;
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}
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if (cpu0_node_has_opp_v2_prop() && !of_match_node(blocklist, np))
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goto create_pdev;
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of_node_put(np);
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return -ENODEV;
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create_pdev:
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of_node_put(np);
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return PTR_ERR_OR_ZERO(platform_device_register_data(NULL, "cpufreq-dt",
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-1, data,
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sizeof(struct cpufreq_dt_platform_data)));
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}
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core_initcall(cpufreq_dt_platdev_init);
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MODULE_LICENSE("GPL");
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