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![Dan Williams](/assets/img/avatar_default.png)
Pick up the driver cleanups identified in preparation for CXL "type-2" (accelerator) device support. The major change here from a conflict generation perspective is the split of 'struct cxl_memdev_state' from the core 'struct cxl_dev_state'. Since an accelerator may not care about all the optional features that are standard on a CXL "type-3" (host-only memory expander) device. A silent conflict also occurs with the move of the endpoint port to be a formal property of a 'struct cxl_memdev' rather than drvdata.
205 lines
6 KiB
C
205 lines
6 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright(c) 2022 Intel Corporation. All rights reserved. */
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#include <linux/libnvdimm.h>
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#include <asm/unaligned.h>
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#include <linux/module.h>
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#include <linux/async.h>
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#include <linux/slab.h>
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#include <linux/memregion.h>
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#include "cxlmem.h"
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#include "cxl.h"
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static unsigned long cxl_pmem_get_security_flags(struct nvdimm *nvdimm,
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enum nvdimm_passphrase_type ptype)
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{
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struct cxl_nvdimm *cxl_nvd = nvdimm_provider_data(nvdimm);
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struct cxl_memdev *cxlmd = cxl_nvd->cxlmd;
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struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlmd->cxlds);
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unsigned long security_flags = 0;
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struct cxl_get_security_output {
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__le32 flags;
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} out;
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struct cxl_mbox_cmd mbox_cmd;
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u32 sec_out;
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int rc;
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mbox_cmd = (struct cxl_mbox_cmd) {
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.opcode = CXL_MBOX_OP_GET_SECURITY_STATE,
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.size_out = sizeof(out),
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.payload_out = &out,
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};
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rc = cxl_internal_send_cmd(mds, &mbox_cmd);
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if (rc < 0)
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return 0;
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sec_out = le32_to_cpu(out.flags);
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/* cache security state */
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mds->security.state = sec_out;
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if (ptype == NVDIMM_MASTER) {
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if (sec_out & CXL_PMEM_SEC_STATE_MASTER_PASS_SET)
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set_bit(NVDIMM_SECURITY_UNLOCKED, &security_flags);
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else
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set_bit(NVDIMM_SECURITY_DISABLED, &security_flags);
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if (sec_out & CXL_PMEM_SEC_STATE_MASTER_PLIMIT)
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set_bit(NVDIMM_SECURITY_FROZEN, &security_flags);
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return security_flags;
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}
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if (sec_out & CXL_PMEM_SEC_STATE_USER_PASS_SET) {
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if (sec_out & CXL_PMEM_SEC_STATE_FROZEN ||
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sec_out & CXL_PMEM_SEC_STATE_USER_PLIMIT)
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set_bit(NVDIMM_SECURITY_FROZEN, &security_flags);
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if (sec_out & CXL_PMEM_SEC_STATE_LOCKED)
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set_bit(NVDIMM_SECURITY_LOCKED, &security_flags);
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else
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set_bit(NVDIMM_SECURITY_UNLOCKED, &security_flags);
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} else {
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set_bit(NVDIMM_SECURITY_DISABLED, &security_flags);
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}
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return security_flags;
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}
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static int cxl_pmem_security_change_key(struct nvdimm *nvdimm,
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const struct nvdimm_key_data *old_data,
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const struct nvdimm_key_data *new_data,
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enum nvdimm_passphrase_type ptype)
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{
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struct cxl_nvdimm *cxl_nvd = nvdimm_provider_data(nvdimm);
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struct cxl_memdev *cxlmd = cxl_nvd->cxlmd;
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struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlmd->cxlds);
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struct cxl_mbox_cmd mbox_cmd;
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struct cxl_set_pass set_pass;
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set_pass = (struct cxl_set_pass) {
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.type = ptype == NVDIMM_MASTER ? CXL_PMEM_SEC_PASS_MASTER :
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CXL_PMEM_SEC_PASS_USER,
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};
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memcpy(set_pass.old_pass, old_data->data, NVDIMM_PASSPHRASE_LEN);
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memcpy(set_pass.new_pass, new_data->data, NVDIMM_PASSPHRASE_LEN);
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mbox_cmd = (struct cxl_mbox_cmd) {
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.opcode = CXL_MBOX_OP_SET_PASSPHRASE,
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.size_in = sizeof(set_pass),
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.payload_in = &set_pass,
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};
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return cxl_internal_send_cmd(mds, &mbox_cmd);
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}
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static int __cxl_pmem_security_disable(struct nvdimm *nvdimm,
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const struct nvdimm_key_data *key_data,
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enum nvdimm_passphrase_type ptype)
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{
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struct cxl_nvdimm *cxl_nvd = nvdimm_provider_data(nvdimm);
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struct cxl_memdev *cxlmd = cxl_nvd->cxlmd;
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struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlmd->cxlds);
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struct cxl_disable_pass dis_pass;
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struct cxl_mbox_cmd mbox_cmd;
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dis_pass = (struct cxl_disable_pass) {
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.type = ptype == NVDIMM_MASTER ? CXL_PMEM_SEC_PASS_MASTER :
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CXL_PMEM_SEC_PASS_USER,
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};
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memcpy(dis_pass.pass, key_data->data, NVDIMM_PASSPHRASE_LEN);
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mbox_cmd = (struct cxl_mbox_cmd) {
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.opcode = CXL_MBOX_OP_DISABLE_PASSPHRASE,
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.size_in = sizeof(dis_pass),
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.payload_in = &dis_pass,
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};
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return cxl_internal_send_cmd(mds, &mbox_cmd);
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}
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static int cxl_pmem_security_disable(struct nvdimm *nvdimm,
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const struct nvdimm_key_data *key_data)
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{
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return __cxl_pmem_security_disable(nvdimm, key_data, NVDIMM_USER);
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}
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static int cxl_pmem_security_disable_master(struct nvdimm *nvdimm,
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const struct nvdimm_key_data *key_data)
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{
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return __cxl_pmem_security_disable(nvdimm, key_data, NVDIMM_MASTER);
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}
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static int cxl_pmem_security_freeze(struct nvdimm *nvdimm)
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{
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struct cxl_nvdimm *cxl_nvd = nvdimm_provider_data(nvdimm);
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struct cxl_memdev *cxlmd = cxl_nvd->cxlmd;
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struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlmd->cxlds);
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struct cxl_mbox_cmd mbox_cmd = {
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.opcode = CXL_MBOX_OP_FREEZE_SECURITY,
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};
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return cxl_internal_send_cmd(mds, &mbox_cmd);
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}
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static int cxl_pmem_security_unlock(struct nvdimm *nvdimm,
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const struct nvdimm_key_data *key_data)
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{
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struct cxl_nvdimm *cxl_nvd = nvdimm_provider_data(nvdimm);
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struct cxl_memdev *cxlmd = cxl_nvd->cxlmd;
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struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlmd->cxlds);
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u8 pass[NVDIMM_PASSPHRASE_LEN];
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struct cxl_mbox_cmd mbox_cmd;
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int rc;
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memcpy(pass, key_data->data, NVDIMM_PASSPHRASE_LEN);
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mbox_cmd = (struct cxl_mbox_cmd) {
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.opcode = CXL_MBOX_OP_UNLOCK,
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.size_in = NVDIMM_PASSPHRASE_LEN,
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.payload_in = pass,
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};
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rc = cxl_internal_send_cmd(mds, &mbox_cmd);
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if (rc < 0)
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return rc;
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return 0;
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}
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static int cxl_pmem_security_passphrase_erase(struct nvdimm *nvdimm,
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const struct nvdimm_key_data *key,
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enum nvdimm_passphrase_type ptype)
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{
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struct cxl_nvdimm *cxl_nvd = nvdimm_provider_data(nvdimm);
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struct cxl_memdev *cxlmd = cxl_nvd->cxlmd;
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struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlmd->cxlds);
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struct cxl_mbox_cmd mbox_cmd;
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struct cxl_pass_erase erase;
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int rc;
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erase = (struct cxl_pass_erase) {
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.type = ptype == NVDIMM_MASTER ? CXL_PMEM_SEC_PASS_MASTER :
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CXL_PMEM_SEC_PASS_USER,
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};
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memcpy(erase.pass, key->data, NVDIMM_PASSPHRASE_LEN);
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mbox_cmd = (struct cxl_mbox_cmd) {
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.opcode = CXL_MBOX_OP_PASSPHRASE_SECURE_ERASE,
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.size_in = sizeof(erase),
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.payload_in = &erase,
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};
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rc = cxl_internal_send_cmd(mds, &mbox_cmd);
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if (rc < 0)
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return rc;
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return 0;
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}
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static const struct nvdimm_security_ops __cxl_security_ops = {
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.get_flags = cxl_pmem_get_security_flags,
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.change_key = cxl_pmem_security_change_key,
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.disable = cxl_pmem_security_disable,
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.freeze = cxl_pmem_security_freeze,
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.unlock = cxl_pmem_security_unlock,
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.erase = cxl_pmem_security_passphrase_erase,
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.disable_master = cxl_pmem_security_disable_master,
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};
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const struct nvdimm_security_ops *cxl_security_ops = &__cxl_security_ops;
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