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![Kees Cook](/assets/img/avatar_default.png)
Prepare for the coming implementation by GCC and Clang of the __counted_by attribute. Flexible array members annotated with __counted_by can have their accesses bounds-checked at run-time checking via CONFIG_UBSAN_BOUNDS (for array indexing) and CONFIG_FORTIFY_SOURCE (for strcpy/memcpy-family functions). As found with Coccinelle[1], add __counted_by for struct uniphier_xdmac_device. [1] https://github.com/kees/kernel-tools/blob/trunk/coccinelle/examples/counted_by.cocci Cc: Vinod Koul <vkoul@kernel.org> Cc: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Cc: Masami Hiramatsu <mhiramat@kernel.org> Cc: dmaengine@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Kees Cook <keescook@chromium.org> Reviewed-by: "Gustavo A. R. Silva" <gustavoars@kernel.org> Link: https://lore.kernel.org/r/20230817235859.49846-20-keescook@chromium.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
611 lines
16 KiB
C
611 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* External DMA controller driver for UniPhier SoCs
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* Copyright 2019 Socionext Inc.
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* Author: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
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*/
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#include <linux/bitops.h>
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#include <linux/bitfield.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_dma.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include "dmaengine.h"
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#include "virt-dma.h"
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#define XDMAC_CH_WIDTH 0x100
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#define XDMAC_TFA 0x08
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#define XDMAC_TFA_MCNT_MASK GENMASK(23, 16)
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#define XDMAC_TFA_MASK GENMASK(5, 0)
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#define XDMAC_SADM 0x10
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#define XDMAC_SADM_STW_MASK GENMASK(25, 24)
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#define XDMAC_SADM_SAM BIT(4)
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#define XDMAC_SADM_SAM_FIXED XDMAC_SADM_SAM
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#define XDMAC_SADM_SAM_INC 0
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#define XDMAC_DADM 0x14
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#define XDMAC_DADM_DTW_MASK XDMAC_SADM_STW_MASK
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#define XDMAC_DADM_DAM XDMAC_SADM_SAM
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#define XDMAC_DADM_DAM_FIXED XDMAC_SADM_SAM_FIXED
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#define XDMAC_DADM_DAM_INC XDMAC_SADM_SAM_INC
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#define XDMAC_EXSAD 0x18
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#define XDMAC_EXDAD 0x1c
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#define XDMAC_SAD 0x20
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#define XDMAC_DAD 0x24
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#define XDMAC_ITS 0x28
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#define XDMAC_ITS_MASK GENMASK(25, 0)
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#define XDMAC_TNUM 0x2c
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#define XDMAC_TNUM_MASK GENMASK(15, 0)
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#define XDMAC_TSS 0x30
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#define XDMAC_TSS_REQ BIT(0)
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#define XDMAC_IEN 0x34
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#define XDMAC_IEN_ERRIEN BIT(1)
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#define XDMAC_IEN_ENDIEN BIT(0)
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#define XDMAC_STAT 0x40
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#define XDMAC_STAT_TENF BIT(0)
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#define XDMAC_IR 0x44
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#define XDMAC_IR_ERRF BIT(1)
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#define XDMAC_IR_ENDF BIT(0)
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#define XDMAC_ID 0x48
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#define XDMAC_ID_ERRIDF BIT(1)
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#define XDMAC_ID_ENDIDF BIT(0)
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#define XDMAC_MAX_CHANS 16
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#define XDMAC_INTERVAL_CLKS 20
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#define XDMAC_MAX_WORDS XDMAC_TNUM_MASK
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/* cut lower bit for maintain alignment of maximum transfer size */
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#define XDMAC_MAX_WORD_SIZE (XDMAC_ITS_MASK & ~GENMASK(3, 0))
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#define UNIPHIER_XDMAC_BUSWIDTHS \
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(BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
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BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
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BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
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BIT(DMA_SLAVE_BUSWIDTH_8_BYTES))
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struct uniphier_xdmac_desc_node {
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dma_addr_t src;
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dma_addr_t dst;
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u32 burst_size;
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u32 nr_burst;
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};
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struct uniphier_xdmac_desc {
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struct virt_dma_desc vd;
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unsigned int nr_node;
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unsigned int cur_node;
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enum dma_transfer_direction dir;
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struct uniphier_xdmac_desc_node nodes[] __counted_by(nr_node);
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};
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struct uniphier_xdmac_chan {
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struct virt_dma_chan vc;
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struct uniphier_xdmac_device *xdev;
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struct uniphier_xdmac_desc *xd;
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void __iomem *reg_ch_base;
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struct dma_slave_config sconfig;
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int id;
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unsigned int req_factor;
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};
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struct uniphier_xdmac_device {
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struct dma_device ddev;
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void __iomem *reg_base;
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int nr_chans;
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struct uniphier_xdmac_chan channels[] __counted_by(nr_chans);
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};
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static struct uniphier_xdmac_chan *
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to_uniphier_xdmac_chan(struct virt_dma_chan *vc)
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{
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return container_of(vc, struct uniphier_xdmac_chan, vc);
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}
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static struct uniphier_xdmac_desc *
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to_uniphier_xdmac_desc(struct virt_dma_desc *vd)
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{
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return container_of(vd, struct uniphier_xdmac_desc, vd);
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}
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/* xc->vc.lock must be held by caller */
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static struct uniphier_xdmac_desc *
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uniphier_xdmac_next_desc(struct uniphier_xdmac_chan *xc)
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{
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struct virt_dma_desc *vd;
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vd = vchan_next_desc(&xc->vc);
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if (!vd)
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return NULL;
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list_del(&vd->node);
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return to_uniphier_xdmac_desc(vd);
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}
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/* xc->vc.lock must be held by caller */
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static void uniphier_xdmac_chan_start(struct uniphier_xdmac_chan *xc,
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struct uniphier_xdmac_desc *xd)
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{
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u32 src_mode, src_width;
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u32 dst_mode, dst_width;
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dma_addr_t src_addr, dst_addr;
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u32 val, its, tnum;
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enum dma_slave_buswidth buswidth;
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src_addr = xd->nodes[xd->cur_node].src;
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dst_addr = xd->nodes[xd->cur_node].dst;
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its = xd->nodes[xd->cur_node].burst_size;
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tnum = xd->nodes[xd->cur_node].nr_burst;
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/*
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* The width of MEM side must be 4 or 8 bytes, that does not
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* affect that of DEV side and transfer size.
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*/
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if (xd->dir == DMA_DEV_TO_MEM) {
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src_mode = XDMAC_SADM_SAM_FIXED;
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buswidth = xc->sconfig.src_addr_width;
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} else {
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src_mode = XDMAC_SADM_SAM_INC;
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buswidth = DMA_SLAVE_BUSWIDTH_8_BYTES;
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}
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src_width = FIELD_PREP(XDMAC_SADM_STW_MASK, __ffs(buswidth));
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if (xd->dir == DMA_MEM_TO_DEV) {
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dst_mode = XDMAC_DADM_DAM_FIXED;
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buswidth = xc->sconfig.dst_addr_width;
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} else {
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dst_mode = XDMAC_DADM_DAM_INC;
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buswidth = DMA_SLAVE_BUSWIDTH_8_BYTES;
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}
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dst_width = FIELD_PREP(XDMAC_DADM_DTW_MASK, __ffs(buswidth));
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/* setup transfer factor */
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val = FIELD_PREP(XDMAC_TFA_MCNT_MASK, XDMAC_INTERVAL_CLKS);
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val |= FIELD_PREP(XDMAC_TFA_MASK, xc->req_factor);
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writel(val, xc->reg_ch_base + XDMAC_TFA);
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/* setup the channel */
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writel(lower_32_bits(src_addr), xc->reg_ch_base + XDMAC_SAD);
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writel(upper_32_bits(src_addr), xc->reg_ch_base + XDMAC_EXSAD);
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writel(lower_32_bits(dst_addr), xc->reg_ch_base + XDMAC_DAD);
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writel(upper_32_bits(dst_addr), xc->reg_ch_base + XDMAC_EXDAD);
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src_mode |= src_width;
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dst_mode |= dst_width;
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writel(src_mode, xc->reg_ch_base + XDMAC_SADM);
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writel(dst_mode, xc->reg_ch_base + XDMAC_DADM);
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writel(its, xc->reg_ch_base + XDMAC_ITS);
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writel(tnum, xc->reg_ch_base + XDMAC_TNUM);
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/* enable interrupt */
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writel(XDMAC_IEN_ENDIEN | XDMAC_IEN_ERRIEN,
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xc->reg_ch_base + XDMAC_IEN);
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/* start XDMAC */
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val = readl(xc->reg_ch_base + XDMAC_TSS);
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val |= XDMAC_TSS_REQ;
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writel(val, xc->reg_ch_base + XDMAC_TSS);
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}
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/* xc->vc.lock must be held by caller */
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static int uniphier_xdmac_chan_stop(struct uniphier_xdmac_chan *xc)
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{
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u32 val;
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/* disable interrupt */
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val = readl(xc->reg_ch_base + XDMAC_IEN);
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val &= ~(XDMAC_IEN_ENDIEN | XDMAC_IEN_ERRIEN);
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writel(val, xc->reg_ch_base + XDMAC_IEN);
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/* stop XDMAC */
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val = readl(xc->reg_ch_base + XDMAC_TSS);
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val &= ~XDMAC_TSS_REQ;
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writel(0, xc->reg_ch_base + XDMAC_TSS);
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/* wait until transfer is stopped */
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return readl_poll_timeout_atomic(xc->reg_ch_base + XDMAC_STAT, val,
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!(val & XDMAC_STAT_TENF), 100, 1000);
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}
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/* xc->vc.lock must be held by caller */
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static void uniphier_xdmac_start(struct uniphier_xdmac_chan *xc)
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{
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struct uniphier_xdmac_desc *xd;
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xd = uniphier_xdmac_next_desc(xc);
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if (xd)
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uniphier_xdmac_chan_start(xc, xd);
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/* set desc to chan regardless of xd is null */
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xc->xd = xd;
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}
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static void uniphier_xdmac_chan_irq(struct uniphier_xdmac_chan *xc)
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{
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u32 stat;
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int ret;
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spin_lock(&xc->vc.lock);
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stat = readl(xc->reg_ch_base + XDMAC_ID);
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if (stat & XDMAC_ID_ERRIDF) {
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ret = uniphier_xdmac_chan_stop(xc);
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if (ret)
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dev_err(xc->xdev->ddev.dev,
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"DMA transfer error with aborting issue\n");
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else
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dev_err(xc->xdev->ddev.dev,
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"DMA transfer error\n");
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} else if ((stat & XDMAC_ID_ENDIDF) && xc->xd) {
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xc->xd->cur_node++;
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if (xc->xd->cur_node >= xc->xd->nr_node) {
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vchan_cookie_complete(&xc->xd->vd);
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uniphier_xdmac_start(xc);
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} else {
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uniphier_xdmac_chan_start(xc, xc->xd);
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}
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}
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/* write bits to clear */
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writel(stat, xc->reg_ch_base + XDMAC_IR);
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spin_unlock(&xc->vc.lock);
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}
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static irqreturn_t uniphier_xdmac_irq_handler(int irq, void *dev_id)
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{
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struct uniphier_xdmac_device *xdev = dev_id;
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int i;
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for (i = 0; i < xdev->nr_chans; i++)
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uniphier_xdmac_chan_irq(&xdev->channels[i]);
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return IRQ_HANDLED;
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}
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static void uniphier_xdmac_free_chan_resources(struct dma_chan *chan)
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{
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vchan_free_chan_resources(to_virt_chan(chan));
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}
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static struct dma_async_tx_descriptor *
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uniphier_xdmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst,
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dma_addr_t src, size_t len, unsigned long flags)
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{
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struct virt_dma_chan *vc = to_virt_chan(chan);
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struct uniphier_xdmac_desc *xd;
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unsigned int nr;
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size_t burst_size, tlen;
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int i;
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if (len > XDMAC_MAX_WORD_SIZE * XDMAC_MAX_WORDS)
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return NULL;
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nr = 1 + len / XDMAC_MAX_WORD_SIZE;
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xd = kzalloc(struct_size(xd, nodes, nr), GFP_NOWAIT);
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if (!xd)
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return NULL;
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xd->nr_node = nr;
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for (i = 0; i < nr; i++) {
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burst_size = min_t(size_t, len, XDMAC_MAX_WORD_SIZE);
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xd->nodes[i].src = src;
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xd->nodes[i].dst = dst;
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xd->nodes[i].burst_size = burst_size;
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xd->nodes[i].nr_burst = len / burst_size;
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tlen = rounddown(len, burst_size);
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src += tlen;
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dst += tlen;
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len -= tlen;
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}
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xd->dir = DMA_MEM_TO_MEM;
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xd->cur_node = 0;
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return vchan_tx_prep(vc, &xd->vd, flags);
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}
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static struct dma_async_tx_descriptor *
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uniphier_xdmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
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unsigned int sg_len,
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enum dma_transfer_direction direction,
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unsigned long flags, void *context)
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{
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struct virt_dma_chan *vc = to_virt_chan(chan);
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struct uniphier_xdmac_chan *xc = to_uniphier_xdmac_chan(vc);
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struct uniphier_xdmac_desc *xd;
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struct scatterlist *sg;
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enum dma_slave_buswidth buswidth;
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u32 maxburst;
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int i;
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if (!is_slave_direction(direction))
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return NULL;
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if (direction == DMA_DEV_TO_MEM) {
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buswidth = xc->sconfig.src_addr_width;
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maxburst = xc->sconfig.src_maxburst;
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} else {
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buswidth = xc->sconfig.dst_addr_width;
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maxburst = xc->sconfig.dst_maxburst;
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}
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if (!maxburst)
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maxburst = 1;
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if (maxburst > xc->xdev->ddev.max_burst) {
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dev_err(xc->xdev->ddev.dev,
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"Exceed maximum number of burst words\n");
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return NULL;
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}
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xd = kzalloc(struct_size(xd, nodes, sg_len), GFP_NOWAIT);
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if (!xd)
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return NULL;
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xd->nr_node = sg_len;
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for_each_sg(sgl, sg, sg_len, i) {
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xd->nodes[i].src = (direction == DMA_DEV_TO_MEM)
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? xc->sconfig.src_addr : sg_dma_address(sg);
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xd->nodes[i].dst = (direction == DMA_MEM_TO_DEV)
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? xc->sconfig.dst_addr : sg_dma_address(sg);
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xd->nodes[i].burst_size = maxburst * buswidth;
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xd->nodes[i].nr_burst =
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sg_dma_len(sg) / xd->nodes[i].burst_size;
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/*
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* Currently transfer that size doesn't align the unit size
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* (the number of burst words * bus-width) is not allowed,
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* because the driver does not support the way to transfer
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* residue size. As a matter of fact, in order to transfer
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* arbitrary size, 'src_maxburst' or 'dst_maxburst' of
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* dma_slave_config must be 1.
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*/
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if (sg_dma_len(sg) % xd->nodes[i].burst_size) {
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dev_err(xc->xdev->ddev.dev,
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"Unaligned transfer size: %d", sg_dma_len(sg));
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kfree(xd);
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return NULL;
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}
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if (xd->nodes[i].nr_burst > XDMAC_MAX_WORDS) {
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dev_err(xc->xdev->ddev.dev,
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"Exceed maximum transfer size");
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kfree(xd);
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return NULL;
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}
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}
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xd->dir = direction;
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xd->cur_node = 0;
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return vchan_tx_prep(vc, &xd->vd, flags);
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}
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static int uniphier_xdmac_slave_config(struct dma_chan *chan,
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struct dma_slave_config *config)
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{
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struct virt_dma_chan *vc = to_virt_chan(chan);
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struct uniphier_xdmac_chan *xc = to_uniphier_xdmac_chan(vc);
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memcpy(&xc->sconfig, config, sizeof(*config));
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return 0;
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}
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static int uniphier_xdmac_terminate_all(struct dma_chan *chan)
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{
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struct virt_dma_chan *vc = to_virt_chan(chan);
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struct uniphier_xdmac_chan *xc = to_uniphier_xdmac_chan(vc);
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unsigned long flags;
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int ret = 0;
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LIST_HEAD(head);
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spin_lock_irqsave(&vc->lock, flags);
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if (xc->xd) {
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vchan_terminate_vdesc(&xc->xd->vd);
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xc->xd = NULL;
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ret = uniphier_xdmac_chan_stop(xc);
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}
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vchan_get_all_descriptors(vc, &head);
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spin_unlock_irqrestore(&vc->lock, flags);
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vchan_dma_desc_free_list(vc, &head);
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return ret;
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}
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static void uniphier_xdmac_synchronize(struct dma_chan *chan)
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{
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vchan_synchronize(to_virt_chan(chan));
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}
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static void uniphier_xdmac_issue_pending(struct dma_chan *chan)
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{
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struct virt_dma_chan *vc = to_virt_chan(chan);
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struct uniphier_xdmac_chan *xc = to_uniphier_xdmac_chan(vc);
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unsigned long flags;
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spin_lock_irqsave(&vc->lock, flags);
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if (vchan_issue_pending(vc) && !xc->xd)
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uniphier_xdmac_start(xc);
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spin_unlock_irqrestore(&vc->lock, flags);
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}
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static void uniphier_xdmac_desc_free(struct virt_dma_desc *vd)
|
|
{
|
|
kfree(to_uniphier_xdmac_desc(vd));
|
|
}
|
|
|
|
static void uniphier_xdmac_chan_init(struct uniphier_xdmac_device *xdev,
|
|
int ch)
|
|
{
|
|
struct uniphier_xdmac_chan *xc = &xdev->channels[ch];
|
|
|
|
xc->xdev = xdev;
|
|
xc->reg_ch_base = xdev->reg_base + XDMAC_CH_WIDTH * ch;
|
|
xc->vc.desc_free = uniphier_xdmac_desc_free;
|
|
|
|
vchan_init(&xc->vc, &xdev->ddev);
|
|
}
|
|
|
|
static struct dma_chan *of_dma_uniphier_xlate(struct of_phandle_args *dma_spec,
|
|
struct of_dma *ofdma)
|
|
{
|
|
struct uniphier_xdmac_device *xdev = ofdma->of_dma_data;
|
|
int chan_id = dma_spec->args[0];
|
|
|
|
if (chan_id >= xdev->nr_chans)
|
|
return NULL;
|
|
|
|
xdev->channels[chan_id].id = chan_id;
|
|
xdev->channels[chan_id].req_factor = dma_spec->args[1];
|
|
|
|
return dma_get_slave_channel(&xdev->channels[chan_id].vc.chan);
|
|
}
|
|
|
|
static int uniphier_xdmac_probe(struct platform_device *pdev)
|
|
{
|
|
struct uniphier_xdmac_device *xdev;
|
|
struct device *dev = &pdev->dev;
|
|
struct dma_device *ddev;
|
|
int irq;
|
|
int nr_chans;
|
|
int i, ret;
|
|
|
|
if (of_property_read_u32(dev->of_node, "dma-channels", &nr_chans))
|
|
return -EINVAL;
|
|
if (nr_chans > XDMAC_MAX_CHANS)
|
|
nr_chans = XDMAC_MAX_CHANS;
|
|
|
|
xdev = devm_kzalloc(dev, struct_size(xdev, channels, nr_chans),
|
|
GFP_KERNEL);
|
|
if (!xdev)
|
|
return -ENOMEM;
|
|
|
|
xdev->nr_chans = nr_chans;
|
|
xdev->reg_base = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(xdev->reg_base))
|
|
return PTR_ERR(xdev->reg_base);
|
|
|
|
ddev = &xdev->ddev;
|
|
ddev->dev = dev;
|
|
dma_cap_zero(ddev->cap_mask);
|
|
dma_cap_set(DMA_MEMCPY, ddev->cap_mask);
|
|
dma_cap_set(DMA_SLAVE, ddev->cap_mask);
|
|
ddev->src_addr_widths = UNIPHIER_XDMAC_BUSWIDTHS;
|
|
ddev->dst_addr_widths = UNIPHIER_XDMAC_BUSWIDTHS;
|
|
ddev->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV) |
|
|
BIT(DMA_MEM_TO_MEM);
|
|
ddev->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
|
|
ddev->max_burst = XDMAC_MAX_WORDS;
|
|
ddev->device_free_chan_resources = uniphier_xdmac_free_chan_resources;
|
|
ddev->device_prep_dma_memcpy = uniphier_xdmac_prep_dma_memcpy;
|
|
ddev->device_prep_slave_sg = uniphier_xdmac_prep_slave_sg;
|
|
ddev->device_config = uniphier_xdmac_slave_config;
|
|
ddev->device_terminate_all = uniphier_xdmac_terminate_all;
|
|
ddev->device_synchronize = uniphier_xdmac_synchronize;
|
|
ddev->device_tx_status = dma_cookie_status;
|
|
ddev->device_issue_pending = uniphier_xdmac_issue_pending;
|
|
INIT_LIST_HEAD(&ddev->channels);
|
|
|
|
for (i = 0; i < nr_chans; i++)
|
|
uniphier_xdmac_chan_init(xdev, i);
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq < 0)
|
|
return irq;
|
|
|
|
ret = devm_request_irq(dev, irq, uniphier_xdmac_irq_handler,
|
|
IRQF_SHARED, "xdmac", xdev);
|
|
if (ret) {
|
|
dev_err(dev, "Failed to request IRQ\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = dma_async_device_register(ddev);
|
|
if (ret) {
|
|
dev_err(dev, "Failed to register XDMA device\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = of_dma_controller_register(dev->of_node,
|
|
of_dma_uniphier_xlate, xdev);
|
|
if (ret) {
|
|
dev_err(dev, "Failed to register XDMA controller\n");
|
|
goto out_unregister_dmac;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, xdev);
|
|
|
|
dev_info(&pdev->dev, "UniPhier XDMAC driver (%d channels)\n",
|
|
nr_chans);
|
|
|
|
return 0;
|
|
|
|
out_unregister_dmac:
|
|
dma_async_device_unregister(ddev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int uniphier_xdmac_remove(struct platform_device *pdev)
|
|
{
|
|
struct uniphier_xdmac_device *xdev = platform_get_drvdata(pdev);
|
|
struct dma_device *ddev = &xdev->ddev;
|
|
struct dma_chan *chan;
|
|
int ret;
|
|
|
|
/*
|
|
* Before reaching here, almost all descriptors have been freed by the
|
|
* ->device_free_chan_resources() hook. However, each channel might
|
|
* be still holding one descriptor that was on-flight at that moment.
|
|
* Terminate it to make sure this hardware is no longer running. Then,
|
|
* free the channel resources once again to avoid memory leak.
|
|
*/
|
|
list_for_each_entry(chan, &ddev->channels, device_node) {
|
|
ret = dmaengine_terminate_sync(chan);
|
|
if (ret)
|
|
return ret;
|
|
uniphier_xdmac_free_chan_resources(chan);
|
|
}
|
|
|
|
of_dma_controller_free(pdev->dev.of_node);
|
|
dma_async_device_unregister(ddev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id uniphier_xdmac_match[] = {
|
|
{ .compatible = "socionext,uniphier-xdmac" },
|
|
{ /* sentinel */ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, uniphier_xdmac_match);
|
|
|
|
static struct platform_driver uniphier_xdmac_driver = {
|
|
.probe = uniphier_xdmac_probe,
|
|
.remove = uniphier_xdmac_remove,
|
|
.driver = {
|
|
.name = "uniphier-xdmac",
|
|
.of_match_table = uniphier_xdmac_match,
|
|
},
|
|
};
|
|
module_platform_driver(uniphier_xdmac_driver);
|
|
|
|
MODULE_AUTHOR("Kunihiko Hayashi <hayashi.kunihiko@socionext.com>");
|
|
MODULE_DESCRIPTION("UniPhier external DMA controller driver");
|
|
MODULE_LICENSE("GPL v2");
|