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![Russ Weight](/assets/img/avatar_default.png)
The FPGA manager class driver data structure is being treated as a managed resource instead of using the standard dev_release call-back function to release the class data structure. This change removes the managed resource code for the freeing of the class data structure and combines the create() and register() functions into a single register() or register_full() function. The register_full() function accepts an info data structure to provide flexibility in passing optional parameters. The register() function supports the current parameter list for users that don't require the use of optional parameters. The devm_fpga_mgr_register() function is retained, and the devm_fpga_mgr_register_full() function is added. Signed-off-by: Russ Weight <russell.h.weight@intel.com> Reviewed-by: Xu Yilun <yilun.xu@intel.com> Acked-by: Xu Yilun <yilun.xu@intel.com> Signed-off-by: Moritz Fischer <mdf@kernel.org>
718 lines
19 KiB
C
718 lines
19 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* FPGA Manager Driver for Altera Arria/Cyclone/Stratix CvP
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*
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* Copyright (C) 2017 DENX Software Engineering
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*
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* Anatolij Gustschin <agust@denx.de>
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*
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* Manage Altera FPGA firmware using PCIe CvP.
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* Firmware must be in binary "rbf" format.
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*/
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/fpga/fpga-mgr.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/sizes.h>
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#define CVP_BAR 0 /* BAR used for data transfer in memory mode */
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#define CVP_DUMMY_WR 244 /* dummy writes to clear CvP state machine */
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#define TIMEOUT_US 2000 /* CVP STATUS timeout for USERMODE polling */
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/* Vendor Specific Extended Capability Registers */
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#define VSE_PCIE_EXT_CAP_ID 0x0
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#define VSE_PCIE_EXT_CAP_ID_VAL 0x000b /* 16bit */
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#define VSE_CVP_STATUS 0x1c /* 32bit */
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#define VSE_CVP_STATUS_CFG_RDY BIT(18) /* CVP_CONFIG_READY */
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#define VSE_CVP_STATUS_CFG_ERR BIT(19) /* CVP_CONFIG_ERROR */
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#define VSE_CVP_STATUS_CVP_EN BIT(20) /* ctrl block is enabling CVP */
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#define VSE_CVP_STATUS_USERMODE BIT(21) /* USERMODE */
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#define VSE_CVP_STATUS_CFG_DONE BIT(23) /* CVP_CONFIG_DONE */
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#define VSE_CVP_STATUS_PLD_CLK_IN_USE BIT(24) /* PLD_CLK_IN_USE */
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#define VSE_CVP_MODE_CTRL 0x20 /* 32bit */
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#define VSE_CVP_MODE_CTRL_CVP_MODE BIT(0) /* CVP (1) or normal mode (0) */
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#define VSE_CVP_MODE_CTRL_HIP_CLK_SEL BIT(1) /* PMA (1) or fabric clock (0) */
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#define VSE_CVP_MODE_CTRL_NUMCLKS_OFF 8 /* NUMCLKS bits offset */
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#define VSE_CVP_MODE_CTRL_NUMCLKS_MASK GENMASK(15, 8)
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#define VSE_CVP_DATA 0x28 /* 32bit */
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#define VSE_CVP_PROG_CTRL 0x2c /* 32bit */
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#define VSE_CVP_PROG_CTRL_CONFIG BIT(0)
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#define VSE_CVP_PROG_CTRL_START_XFER BIT(1)
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#define VSE_CVP_PROG_CTRL_MASK GENMASK(1, 0)
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#define VSE_UNCOR_ERR_STATUS 0x34 /* 32bit */
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#define VSE_UNCOR_ERR_CVP_CFG_ERR BIT(5) /* CVP_CONFIG_ERROR_LATCHED */
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#define V1_VSEC_OFFSET 0x200 /* Vendor Specific Offset V1 */
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/* V2 Defines */
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#define VSE_CVP_TX_CREDITS 0x49 /* 8bit */
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#define V2_CREDIT_TIMEOUT_US 20000
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#define V2_CHECK_CREDIT_US 10
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#define V2_POLL_TIMEOUT_US 1000000
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#define V2_USER_TIMEOUT_US 500000
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#define V1_POLL_TIMEOUT_US 10
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#define DRV_NAME "altera-cvp"
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#define ALTERA_CVP_MGR_NAME "Altera CvP FPGA Manager"
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/* Write block sizes */
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#define ALTERA_CVP_V1_SIZE 4
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#define ALTERA_CVP_V2_SIZE 4096
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/* Optional CvP config error status check for debugging */
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static bool altera_cvp_chkcfg;
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struct cvp_priv;
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struct altera_cvp_conf {
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struct fpga_manager *mgr;
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struct pci_dev *pci_dev;
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void __iomem *map;
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void (*write_data)(struct altera_cvp_conf *conf,
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u32 data);
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char mgr_name[64];
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u8 numclks;
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u32 sent_packets;
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u32 vsec_offset;
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const struct cvp_priv *priv;
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};
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struct cvp_priv {
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void (*switch_clk)(struct altera_cvp_conf *conf);
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int (*clear_state)(struct altera_cvp_conf *conf);
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int (*wait_credit)(struct fpga_manager *mgr, u32 blocks);
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size_t block_size;
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int poll_time_us;
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int user_time_us;
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};
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static int altera_read_config_byte(struct altera_cvp_conf *conf,
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int where, u8 *val)
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{
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return pci_read_config_byte(conf->pci_dev, conf->vsec_offset + where,
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val);
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}
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static int altera_read_config_dword(struct altera_cvp_conf *conf,
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int where, u32 *val)
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{
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return pci_read_config_dword(conf->pci_dev, conf->vsec_offset + where,
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val);
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}
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static int altera_write_config_dword(struct altera_cvp_conf *conf,
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int where, u32 val)
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{
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return pci_write_config_dword(conf->pci_dev, conf->vsec_offset + where,
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val);
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}
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static enum fpga_mgr_states altera_cvp_state(struct fpga_manager *mgr)
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{
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struct altera_cvp_conf *conf = mgr->priv;
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u32 status;
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altera_read_config_dword(conf, VSE_CVP_STATUS, &status);
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if (status & VSE_CVP_STATUS_CFG_DONE)
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return FPGA_MGR_STATE_OPERATING;
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if (status & VSE_CVP_STATUS_CVP_EN)
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return FPGA_MGR_STATE_POWER_UP;
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return FPGA_MGR_STATE_UNKNOWN;
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}
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static void altera_cvp_write_data_iomem(struct altera_cvp_conf *conf, u32 val)
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{
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writel(val, conf->map);
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}
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static void altera_cvp_write_data_config(struct altera_cvp_conf *conf, u32 val)
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{
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pci_write_config_dword(conf->pci_dev, conf->vsec_offset + VSE_CVP_DATA,
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val);
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}
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/* switches between CvP clock and internal clock */
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static void altera_cvp_dummy_write(struct altera_cvp_conf *conf)
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{
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unsigned int i;
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u32 val;
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/* set 1 CVP clock cycle for every CVP Data Register Write */
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altera_read_config_dword(conf, VSE_CVP_MODE_CTRL, &val);
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val &= ~VSE_CVP_MODE_CTRL_NUMCLKS_MASK;
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val |= 1 << VSE_CVP_MODE_CTRL_NUMCLKS_OFF;
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altera_write_config_dword(conf, VSE_CVP_MODE_CTRL, val);
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for (i = 0; i < CVP_DUMMY_WR; i++)
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conf->write_data(conf, 0); /* dummy data, could be any value */
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}
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static int altera_cvp_wait_status(struct altera_cvp_conf *conf, u32 status_mask,
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u32 status_val, int timeout_us)
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{
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unsigned int retries;
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u32 val;
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retries = timeout_us / 10;
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if (timeout_us % 10)
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retries++;
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do {
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altera_read_config_dword(conf, VSE_CVP_STATUS, &val);
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if ((val & status_mask) == status_val)
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return 0;
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/* use small usleep value to re-check and break early */
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usleep_range(10, 11);
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} while (--retries);
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return -ETIMEDOUT;
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}
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static int altera_cvp_chk_error(struct fpga_manager *mgr, size_t bytes)
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{
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struct altera_cvp_conf *conf = mgr->priv;
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u32 val;
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int ret;
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/* STEP 10 (optional) - check CVP_CONFIG_ERROR flag */
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ret = altera_read_config_dword(conf, VSE_CVP_STATUS, &val);
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if (ret || (val & VSE_CVP_STATUS_CFG_ERR)) {
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dev_err(&mgr->dev, "CVP_CONFIG_ERROR after %zu bytes!\n",
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bytes);
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return -EPROTO;
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}
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return 0;
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}
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/*
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* CvP Version2 Functions
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* Recent Intel FPGAs use a credit mechanism to throttle incoming
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* bitstreams and a different method of clearing the state.
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*/
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static int altera_cvp_v2_clear_state(struct altera_cvp_conf *conf)
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{
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u32 val;
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int ret;
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/* Clear the START_XFER and CVP_CONFIG bits */
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ret = altera_read_config_dword(conf, VSE_CVP_PROG_CTRL, &val);
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if (ret) {
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dev_err(&conf->pci_dev->dev,
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"Error reading CVP Program Control Register\n");
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return ret;
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}
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val &= ~VSE_CVP_PROG_CTRL_MASK;
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ret = altera_write_config_dword(conf, VSE_CVP_PROG_CTRL, val);
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if (ret) {
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dev_err(&conf->pci_dev->dev,
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"Error writing CVP Program Control Register\n");
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return ret;
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}
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return altera_cvp_wait_status(conf, VSE_CVP_STATUS_CFG_RDY, 0,
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conf->priv->poll_time_us);
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}
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static int altera_cvp_v2_wait_for_credit(struct fpga_manager *mgr,
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u32 blocks)
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{
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u32 timeout = V2_CREDIT_TIMEOUT_US / V2_CHECK_CREDIT_US;
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struct altera_cvp_conf *conf = mgr->priv;
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int ret;
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u8 val;
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do {
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ret = altera_read_config_byte(conf, VSE_CVP_TX_CREDITS, &val);
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if (ret) {
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dev_err(&conf->pci_dev->dev,
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"Error reading CVP Credit Register\n");
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return ret;
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}
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/* Return if there is space in FIFO */
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if (val - (u8)conf->sent_packets)
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return 0;
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ret = altera_cvp_chk_error(mgr, blocks * ALTERA_CVP_V2_SIZE);
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if (ret) {
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dev_err(&conf->pci_dev->dev,
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"CE Bit error credit reg[0x%x]:sent[0x%x]\n",
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val, conf->sent_packets);
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return -EAGAIN;
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}
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/* Limit the check credit byte traffic */
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usleep_range(V2_CHECK_CREDIT_US, V2_CHECK_CREDIT_US + 1);
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} while (timeout--);
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dev_err(&conf->pci_dev->dev, "Timeout waiting for credit\n");
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return -ETIMEDOUT;
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}
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static int altera_cvp_send_block(struct altera_cvp_conf *conf,
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const u32 *data, size_t len)
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{
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u32 mask, words = len / sizeof(u32);
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int i, remainder;
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for (i = 0; i < words; i++)
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conf->write_data(conf, *data++);
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/* write up to 3 trailing bytes, if any */
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remainder = len % sizeof(u32);
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if (remainder) {
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mask = BIT(remainder * 8) - 1;
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if (mask)
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conf->write_data(conf, *data & mask);
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}
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return 0;
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}
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static int altera_cvp_teardown(struct fpga_manager *mgr,
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struct fpga_image_info *info)
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{
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struct altera_cvp_conf *conf = mgr->priv;
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int ret;
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u32 val;
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/* STEP 12 - reset START_XFER bit */
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altera_read_config_dword(conf, VSE_CVP_PROG_CTRL, &val);
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val &= ~VSE_CVP_PROG_CTRL_START_XFER;
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altera_write_config_dword(conf, VSE_CVP_PROG_CTRL, val);
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/* STEP 13 - reset CVP_CONFIG bit */
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val &= ~VSE_CVP_PROG_CTRL_CONFIG;
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altera_write_config_dword(conf, VSE_CVP_PROG_CTRL, val);
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/*
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* STEP 14
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* - set CVP_NUMCLKS to 1 and then issue CVP_DUMMY_WR dummy
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* writes to the HIP
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*/
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if (conf->priv->switch_clk)
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conf->priv->switch_clk(conf);
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/* STEP 15 - poll CVP_CONFIG_READY bit for 0 with 10us timeout */
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ret = altera_cvp_wait_status(conf, VSE_CVP_STATUS_CFG_RDY, 0,
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conf->priv->poll_time_us);
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if (ret)
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dev_err(&mgr->dev, "CFG_RDY == 0 timeout\n");
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return ret;
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}
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static int altera_cvp_write_init(struct fpga_manager *mgr,
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struct fpga_image_info *info,
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const char *buf, size_t count)
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{
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struct altera_cvp_conf *conf = mgr->priv;
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u32 iflags, val;
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int ret;
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iflags = info ? info->flags : 0;
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if (iflags & FPGA_MGR_PARTIAL_RECONFIG) {
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dev_err(&mgr->dev, "Partial reconfiguration not supported.\n");
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return -EINVAL;
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}
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/* Determine allowed clock to data ratio */
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if (iflags & FPGA_MGR_COMPRESSED_BITSTREAM)
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conf->numclks = 8; /* ratio for all compressed images */
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else if (iflags & FPGA_MGR_ENCRYPTED_BITSTREAM)
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conf->numclks = 4; /* for uncompressed and encrypted images */
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else
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conf->numclks = 1; /* for uncompressed and unencrypted images */
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/* STEP 1 - read CVP status and check CVP_EN flag */
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altera_read_config_dword(conf, VSE_CVP_STATUS, &val);
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if (!(val & VSE_CVP_STATUS_CVP_EN)) {
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dev_err(&mgr->dev, "CVP mode off: 0x%04x\n", val);
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return -ENODEV;
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}
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if (val & VSE_CVP_STATUS_CFG_RDY) {
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dev_warn(&mgr->dev, "CvP already started, tear down first\n");
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ret = altera_cvp_teardown(mgr, info);
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if (ret)
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return ret;
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}
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/*
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* STEP 2
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* - set HIP_CLK_SEL and CVP_MODE (must be set in the order mentioned)
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*/
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/* switch from fabric to PMA clock */
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altera_read_config_dword(conf, VSE_CVP_MODE_CTRL, &val);
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val |= VSE_CVP_MODE_CTRL_HIP_CLK_SEL;
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altera_write_config_dword(conf, VSE_CVP_MODE_CTRL, val);
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/* set CVP mode */
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altera_read_config_dword(conf, VSE_CVP_MODE_CTRL, &val);
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val |= VSE_CVP_MODE_CTRL_CVP_MODE;
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altera_write_config_dword(conf, VSE_CVP_MODE_CTRL, val);
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/*
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* STEP 3
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* - set CVP_NUMCLKS to 1 and issue CVP_DUMMY_WR dummy writes to the HIP
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*/
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if (conf->priv->switch_clk)
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conf->priv->switch_clk(conf);
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if (conf->priv->clear_state) {
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ret = conf->priv->clear_state(conf);
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if (ret) {
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dev_err(&mgr->dev, "Problem clearing out state\n");
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return ret;
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}
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}
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conf->sent_packets = 0;
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/* STEP 4 - set CVP_CONFIG bit */
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altera_read_config_dword(conf, VSE_CVP_PROG_CTRL, &val);
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/* request control block to begin transfer using CVP */
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val |= VSE_CVP_PROG_CTRL_CONFIG;
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altera_write_config_dword(conf, VSE_CVP_PROG_CTRL, val);
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/* STEP 5 - poll CVP_CONFIG READY for 1 with timeout */
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ret = altera_cvp_wait_status(conf, VSE_CVP_STATUS_CFG_RDY,
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VSE_CVP_STATUS_CFG_RDY,
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conf->priv->poll_time_us);
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if (ret) {
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dev_warn(&mgr->dev, "CFG_RDY == 1 timeout\n");
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return ret;
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}
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/*
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* STEP 6
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* - set CVP_NUMCLKS to 1 and issue CVP_DUMMY_WR dummy writes to the HIP
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*/
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if (conf->priv->switch_clk)
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conf->priv->switch_clk(conf);
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if (altera_cvp_chkcfg) {
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ret = altera_cvp_chk_error(mgr, 0);
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if (ret) {
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dev_warn(&mgr->dev, "CFG_RDY == 1 timeout\n");
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return ret;
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}
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}
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/* STEP 7 - set START_XFER */
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altera_read_config_dword(conf, VSE_CVP_PROG_CTRL, &val);
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val |= VSE_CVP_PROG_CTRL_START_XFER;
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altera_write_config_dword(conf, VSE_CVP_PROG_CTRL, val);
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/* STEP 8 - start transfer (set CVP_NUMCLKS for bitstream) */
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if (conf->priv->switch_clk) {
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altera_read_config_dword(conf, VSE_CVP_MODE_CTRL, &val);
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val &= ~VSE_CVP_MODE_CTRL_NUMCLKS_MASK;
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val |= conf->numclks << VSE_CVP_MODE_CTRL_NUMCLKS_OFF;
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altera_write_config_dword(conf, VSE_CVP_MODE_CTRL, val);
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}
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return 0;
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}
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static int altera_cvp_write(struct fpga_manager *mgr, const char *buf,
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size_t count)
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{
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struct altera_cvp_conf *conf = mgr->priv;
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size_t done, remaining, len;
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const u32 *data;
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int status = 0;
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/* STEP 9 - write 32-bit data from RBF file to CVP data register */
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data = (u32 *)buf;
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remaining = count;
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done = 0;
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while (remaining) {
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/* Use credit throttling if available */
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if (conf->priv->wait_credit) {
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status = conf->priv->wait_credit(mgr, done);
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if (status) {
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dev_err(&conf->pci_dev->dev,
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"Wait Credit ERR: 0x%x\n", status);
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return status;
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}
|
|
}
|
|
|
|
len = min(conf->priv->block_size, remaining);
|
|
altera_cvp_send_block(conf, data, len);
|
|
data += len / sizeof(u32);
|
|
done += len;
|
|
remaining -= len;
|
|
conf->sent_packets++;
|
|
|
|
/*
|
|
* STEP 10 (optional) and STEP 11
|
|
* - check error flag
|
|
* - loop until data transfer completed
|
|
* Config images can be huge (more than 40 MiB), so
|
|
* only check after a new 4k data block has been written.
|
|
* This reduces the number of checks and speeds up the
|
|
* configuration process.
|
|
*/
|
|
if (altera_cvp_chkcfg && !(done % SZ_4K)) {
|
|
status = altera_cvp_chk_error(mgr, done);
|
|
if (status < 0)
|
|
return status;
|
|
}
|
|
}
|
|
|
|
if (altera_cvp_chkcfg)
|
|
status = altera_cvp_chk_error(mgr, count);
|
|
|
|
return status;
|
|
}
|
|
|
|
static int altera_cvp_write_complete(struct fpga_manager *mgr,
|
|
struct fpga_image_info *info)
|
|
{
|
|
struct altera_cvp_conf *conf = mgr->priv;
|
|
u32 mask, val;
|
|
int ret;
|
|
|
|
ret = altera_cvp_teardown(mgr, info);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* STEP 16 - check CVP_CONFIG_ERROR_LATCHED bit */
|
|
altera_read_config_dword(conf, VSE_UNCOR_ERR_STATUS, &val);
|
|
if (val & VSE_UNCOR_ERR_CVP_CFG_ERR) {
|
|
dev_err(&mgr->dev, "detected CVP_CONFIG_ERROR_LATCHED!\n");
|
|
return -EPROTO;
|
|
}
|
|
|
|
/* STEP 17 - reset CVP_MODE and HIP_CLK_SEL bit */
|
|
altera_read_config_dword(conf, VSE_CVP_MODE_CTRL, &val);
|
|
val &= ~VSE_CVP_MODE_CTRL_HIP_CLK_SEL;
|
|
val &= ~VSE_CVP_MODE_CTRL_CVP_MODE;
|
|
altera_write_config_dword(conf, VSE_CVP_MODE_CTRL, val);
|
|
|
|
/* STEP 18 - poll PLD_CLK_IN_USE and USER_MODE bits */
|
|
mask = VSE_CVP_STATUS_PLD_CLK_IN_USE | VSE_CVP_STATUS_USERMODE;
|
|
ret = altera_cvp_wait_status(conf, mask, mask,
|
|
conf->priv->user_time_us);
|
|
if (ret)
|
|
dev_err(&mgr->dev, "PLD_CLK_IN_USE|USERMODE timeout\n");
|
|
|
|
return ret;
|
|
}
|
|
|
|
static const struct fpga_manager_ops altera_cvp_ops = {
|
|
.state = altera_cvp_state,
|
|
.write_init = altera_cvp_write_init,
|
|
.write = altera_cvp_write,
|
|
.write_complete = altera_cvp_write_complete,
|
|
};
|
|
|
|
static const struct cvp_priv cvp_priv_v1 = {
|
|
.switch_clk = altera_cvp_dummy_write,
|
|
.block_size = ALTERA_CVP_V1_SIZE,
|
|
.poll_time_us = V1_POLL_TIMEOUT_US,
|
|
.user_time_us = TIMEOUT_US,
|
|
};
|
|
|
|
static const struct cvp_priv cvp_priv_v2 = {
|
|
.clear_state = altera_cvp_v2_clear_state,
|
|
.wait_credit = altera_cvp_v2_wait_for_credit,
|
|
.block_size = ALTERA_CVP_V2_SIZE,
|
|
.poll_time_us = V2_POLL_TIMEOUT_US,
|
|
.user_time_us = V2_USER_TIMEOUT_US,
|
|
};
|
|
|
|
static ssize_t chkcfg_show(struct device_driver *dev, char *buf)
|
|
{
|
|
return snprintf(buf, 3, "%d\n", altera_cvp_chkcfg);
|
|
}
|
|
|
|
static ssize_t chkcfg_store(struct device_driver *drv, const char *buf,
|
|
size_t count)
|
|
{
|
|
int ret;
|
|
|
|
ret = kstrtobool(buf, &altera_cvp_chkcfg);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return count;
|
|
}
|
|
|
|
static DRIVER_ATTR_RW(chkcfg);
|
|
|
|
static int altera_cvp_probe(struct pci_dev *pdev,
|
|
const struct pci_device_id *dev_id);
|
|
static void altera_cvp_remove(struct pci_dev *pdev);
|
|
|
|
static struct pci_device_id altera_cvp_id_tbl[] = {
|
|
{ PCI_VDEVICE(ALTERA, PCI_ANY_ID) },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(pci, altera_cvp_id_tbl);
|
|
|
|
static struct pci_driver altera_cvp_driver = {
|
|
.name = DRV_NAME,
|
|
.id_table = altera_cvp_id_tbl,
|
|
.probe = altera_cvp_probe,
|
|
.remove = altera_cvp_remove,
|
|
};
|
|
|
|
static int altera_cvp_probe(struct pci_dev *pdev,
|
|
const struct pci_device_id *dev_id)
|
|
{
|
|
struct altera_cvp_conf *conf;
|
|
struct fpga_manager *mgr;
|
|
int ret, offset;
|
|
u16 cmd, val;
|
|
u32 regval;
|
|
|
|
/* Discover the Vendor Specific Offset for this device */
|
|
offset = pci_find_next_ext_capability(pdev, 0, PCI_EXT_CAP_ID_VNDR);
|
|
if (!offset) {
|
|
dev_err(&pdev->dev, "No Vendor Specific Offset.\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
/*
|
|
* First check if this is the expected FPGA device. PCI config
|
|
* space access works without enabling the PCI device, memory
|
|
* space access is enabled further down.
|
|
*/
|
|
pci_read_config_word(pdev, offset + VSE_PCIE_EXT_CAP_ID, &val);
|
|
if (val != VSE_PCIE_EXT_CAP_ID_VAL) {
|
|
dev_err(&pdev->dev, "Wrong EXT_CAP_ID value 0x%x\n", val);
|
|
return -ENODEV;
|
|
}
|
|
|
|
pci_read_config_dword(pdev, offset + VSE_CVP_STATUS, ®val);
|
|
if (!(regval & VSE_CVP_STATUS_CVP_EN)) {
|
|
dev_err(&pdev->dev,
|
|
"CVP is disabled for this device: CVP_STATUS Reg 0x%x\n",
|
|
regval);
|
|
return -ENODEV;
|
|
}
|
|
|
|
conf = devm_kzalloc(&pdev->dev, sizeof(*conf), GFP_KERNEL);
|
|
if (!conf)
|
|
return -ENOMEM;
|
|
|
|
conf->vsec_offset = offset;
|
|
|
|
/*
|
|
* Enable memory BAR access. We cannot use pci_enable_device() here
|
|
* because it will make the driver unusable with FPGA devices that
|
|
* have additional big IOMEM resources (e.g. 4GiB BARs) on 32-bit
|
|
* platform. Such BARs will not have an assigned address range and
|
|
* pci_enable_device() will fail, complaining about not claimed BAR,
|
|
* even if the concerned BAR is not needed for FPGA configuration
|
|
* at all. Thus, enable the device via PCI config space command.
|
|
*/
|
|
pci_read_config_word(pdev, PCI_COMMAND, &cmd);
|
|
if (!(cmd & PCI_COMMAND_MEMORY)) {
|
|
cmd |= PCI_COMMAND_MEMORY;
|
|
pci_write_config_word(pdev, PCI_COMMAND, cmd);
|
|
}
|
|
|
|
ret = pci_request_region(pdev, CVP_BAR, "CVP");
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Requesting CVP BAR region failed\n");
|
|
goto err_disable;
|
|
}
|
|
|
|
conf->pci_dev = pdev;
|
|
conf->write_data = altera_cvp_write_data_iomem;
|
|
|
|
if (conf->vsec_offset == V1_VSEC_OFFSET)
|
|
conf->priv = &cvp_priv_v1;
|
|
else
|
|
conf->priv = &cvp_priv_v2;
|
|
|
|
conf->map = pci_iomap(pdev, CVP_BAR, 0);
|
|
if (!conf->map) {
|
|
dev_warn(&pdev->dev, "Mapping CVP BAR failed\n");
|
|
conf->write_data = altera_cvp_write_data_config;
|
|
}
|
|
|
|
snprintf(conf->mgr_name, sizeof(conf->mgr_name), "%s @%s",
|
|
ALTERA_CVP_MGR_NAME, pci_name(pdev));
|
|
|
|
mgr = fpga_mgr_register(&pdev->dev, conf->mgr_name,
|
|
&altera_cvp_ops, conf);
|
|
if (IS_ERR(mgr)) {
|
|
ret = PTR_ERR(mgr);
|
|
goto err_unmap;
|
|
}
|
|
|
|
pci_set_drvdata(pdev, mgr);
|
|
|
|
return 0;
|
|
|
|
err_unmap:
|
|
if (conf->map)
|
|
pci_iounmap(pdev, conf->map);
|
|
pci_release_region(pdev, CVP_BAR);
|
|
err_disable:
|
|
cmd &= ~PCI_COMMAND_MEMORY;
|
|
pci_write_config_word(pdev, PCI_COMMAND, cmd);
|
|
return ret;
|
|
}
|
|
|
|
static void altera_cvp_remove(struct pci_dev *pdev)
|
|
{
|
|
struct fpga_manager *mgr = pci_get_drvdata(pdev);
|
|
struct altera_cvp_conf *conf = mgr->priv;
|
|
u16 cmd;
|
|
|
|
fpga_mgr_unregister(mgr);
|
|
if (conf->map)
|
|
pci_iounmap(pdev, conf->map);
|
|
pci_release_region(pdev, CVP_BAR);
|
|
pci_read_config_word(pdev, PCI_COMMAND, &cmd);
|
|
cmd &= ~PCI_COMMAND_MEMORY;
|
|
pci_write_config_word(pdev, PCI_COMMAND, cmd);
|
|
}
|
|
|
|
static int __init altera_cvp_init(void)
|
|
{
|
|
int ret;
|
|
|
|
ret = pci_register_driver(&altera_cvp_driver);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = driver_create_file(&altera_cvp_driver.driver,
|
|
&driver_attr_chkcfg);
|
|
if (ret)
|
|
pr_warn("Can't create sysfs chkcfg file\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void __exit altera_cvp_exit(void)
|
|
{
|
|
driver_remove_file(&altera_cvp_driver.driver, &driver_attr_chkcfg);
|
|
pci_unregister_driver(&altera_cvp_driver);
|
|
}
|
|
|
|
module_init(altera_cvp_init);
|
|
module_exit(altera_cvp_exit);
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_AUTHOR("Anatolij Gustschin <agust@denx.de>");
|
|
MODULE_DESCRIPTION("Module to load Altera FPGA over CvP");
|