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![Russ Weight](/assets/img/avatar_default.png)
The FPGA manager class driver data structure is being treated as a managed resource instead of using the standard dev_release call-back function to release the class data structure. This change removes the managed resource code for the freeing of the class data structure and combines the create() and register() functions into a single register() or register_full() function. The register_full() function accepts an info data structure to provide flexibility in passing optional parameters. The register() function supports the current parameter list for users that don't require the use of optional parameters. The devm_fpga_mgr_register() function is retained, and the devm_fpga_mgr_register_full() function is added. Signed-off-by: Russ Weight <russell.h.weight@intel.com> Reviewed-by: Xu Yilun <yilun.xu@intel.com> Acked-by: Xu Yilun <yilun.xu@intel.com> Signed-off-by: Moritz Fischer <mdf@kernel.org>
211 lines
5.3 KiB
C
211 lines
5.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* FPGA Manager Driver for Lattice iCE40.
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*
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* Copyright (c) 2016 Joel Holdsworth
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*
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* This driver adds support to the FPGA manager for configuring the SRAM of
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* Lattice iCE40 FPGAs through slave SPI.
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*/
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#include <linux/fpga/fpga-mgr.h>
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#include <linux/gpio/consumer.h>
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#include <linux/module.h>
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#include <linux/of_gpio.h>
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#include <linux/spi/spi.h>
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#include <linux/stringify.h>
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#define ICE40_SPI_MAX_SPEED 25000000 /* Hz */
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#define ICE40_SPI_MIN_SPEED 1000000 /* Hz */
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#define ICE40_SPI_RESET_DELAY 1 /* us (>200ns) */
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#define ICE40_SPI_HOUSEKEEPING_DELAY 1200 /* us */
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#define ICE40_SPI_NUM_ACTIVATION_BYTES DIV_ROUND_UP(49, 8)
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struct ice40_fpga_priv {
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struct spi_device *dev;
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struct gpio_desc *reset;
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struct gpio_desc *cdone;
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};
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static enum fpga_mgr_states ice40_fpga_ops_state(struct fpga_manager *mgr)
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{
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struct ice40_fpga_priv *priv = mgr->priv;
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return gpiod_get_value(priv->cdone) ? FPGA_MGR_STATE_OPERATING :
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FPGA_MGR_STATE_UNKNOWN;
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}
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static int ice40_fpga_ops_write_init(struct fpga_manager *mgr,
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struct fpga_image_info *info,
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const char *buf, size_t count)
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{
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struct ice40_fpga_priv *priv = mgr->priv;
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struct spi_device *dev = priv->dev;
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struct spi_message message;
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struct spi_transfer assert_cs_then_reset_delay = {
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.cs_change = 1,
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.delay = {
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.value = ICE40_SPI_RESET_DELAY,
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.unit = SPI_DELAY_UNIT_USECS
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}
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};
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struct spi_transfer housekeeping_delay_then_release_cs = {
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.delay = {
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.value = ICE40_SPI_HOUSEKEEPING_DELAY,
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.unit = SPI_DELAY_UNIT_USECS
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}
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};
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int ret;
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if ((info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {
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dev_err(&dev->dev,
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"Partial reconfiguration is not supported\n");
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return -ENOTSUPP;
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}
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/* Lock the bus, assert CRESET_B and SS_B and delay >200ns */
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spi_bus_lock(dev->master);
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gpiod_set_value(priv->reset, 1);
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spi_message_init(&message);
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spi_message_add_tail(&assert_cs_then_reset_delay, &message);
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ret = spi_sync_locked(dev, &message);
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/* Come out of reset */
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gpiod_set_value(priv->reset, 0);
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/* Abort if the chip-select failed */
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if (ret)
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goto fail;
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/* Check CDONE is de-asserted i.e. the FPGA is reset */
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if (gpiod_get_value(priv->cdone)) {
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dev_err(&dev->dev, "Device reset failed, CDONE is asserted\n");
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ret = -EIO;
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goto fail;
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}
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/* Wait for the housekeeping to complete, and release SS_B */
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spi_message_init(&message);
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spi_message_add_tail(&housekeeping_delay_then_release_cs, &message);
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ret = spi_sync_locked(dev, &message);
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fail:
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spi_bus_unlock(dev->master);
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return ret;
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}
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static int ice40_fpga_ops_write(struct fpga_manager *mgr,
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const char *buf, size_t count)
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{
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struct ice40_fpga_priv *priv = mgr->priv;
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return spi_write(priv->dev, buf, count);
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}
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static int ice40_fpga_ops_write_complete(struct fpga_manager *mgr,
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struct fpga_image_info *info)
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{
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struct ice40_fpga_priv *priv = mgr->priv;
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struct spi_device *dev = priv->dev;
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const u8 padding[ICE40_SPI_NUM_ACTIVATION_BYTES] = {0};
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/* Check CDONE is asserted */
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if (!gpiod_get_value(priv->cdone)) {
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dev_err(&dev->dev,
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"CDONE was not asserted after firmware transfer\n");
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return -EIO;
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}
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/* Send of zero-padding to activate the firmware */
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return spi_write(dev, padding, sizeof(padding));
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}
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static const struct fpga_manager_ops ice40_fpga_ops = {
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.state = ice40_fpga_ops_state,
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.write_init = ice40_fpga_ops_write_init,
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.write = ice40_fpga_ops_write,
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.write_complete = ice40_fpga_ops_write_complete,
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};
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static int ice40_fpga_probe(struct spi_device *spi)
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{
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struct device *dev = &spi->dev;
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struct ice40_fpga_priv *priv;
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struct fpga_manager *mgr;
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int ret;
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priv = devm_kzalloc(&spi->dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->dev = spi;
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/* Check board setup data. */
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if (spi->max_speed_hz > ICE40_SPI_MAX_SPEED) {
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dev_err(dev, "SPI speed is too high, maximum speed is "
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__stringify(ICE40_SPI_MAX_SPEED) "\n");
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return -EINVAL;
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}
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if (spi->max_speed_hz < ICE40_SPI_MIN_SPEED) {
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dev_err(dev, "SPI speed is too low, minimum speed is "
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__stringify(ICE40_SPI_MIN_SPEED) "\n");
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return -EINVAL;
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}
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if (spi->mode & SPI_CPHA) {
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dev_err(dev, "Bad SPI mode, CPHA not supported\n");
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return -EINVAL;
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}
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/* Set up the GPIOs */
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priv->cdone = devm_gpiod_get(dev, "cdone", GPIOD_IN);
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if (IS_ERR(priv->cdone)) {
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ret = PTR_ERR(priv->cdone);
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dev_err(dev, "Failed to get CDONE GPIO: %d\n", ret);
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return ret;
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}
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priv->reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
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if (IS_ERR(priv->reset)) {
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ret = PTR_ERR(priv->reset);
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dev_err(dev, "Failed to get CRESET_B GPIO: %d\n", ret);
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return ret;
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}
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mgr = devm_fpga_mgr_register(dev, "Lattice iCE40 FPGA Manager",
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&ice40_fpga_ops, priv);
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return PTR_ERR_OR_ZERO(mgr);
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}
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static const struct of_device_id ice40_fpga_of_match[] = {
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{ .compatible = "lattice,ice40-fpga-mgr", },
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{},
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};
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MODULE_DEVICE_TABLE(of, ice40_fpga_of_match);
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static const struct spi_device_id ice40_fpga_spi_ids[] = {
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{ .name = "ice40-fpga-mgr", },
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{},
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};
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MODULE_DEVICE_TABLE(spi, ice40_fpga_spi_ids);
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static struct spi_driver ice40_fpga_driver = {
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.probe = ice40_fpga_probe,
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.driver = {
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.name = "ice40spi",
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.of_match_table = of_match_ptr(ice40_fpga_of_match),
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},
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.id_table = ice40_fpga_spi_ids,
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};
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module_spi_driver(ice40_fpga_driver);
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MODULE_AUTHOR("Joel Holdsworth <joel@airwebreathe.org.uk>");
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MODULE_DESCRIPTION("Lattice iCE40 FPGA Manager");
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MODULE_LICENSE("GPL v2");
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