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![Pali Rohár](/assets/img/avatar_default.png)
mvebu and aardvark HW have PCIe capabilities on different offset in PCI config space. Extend pci-bridge-emul.c code to allow setting custom driver custom value where PCIe capabilities starts. With this change PCIe capabilities of both drivers are reported at the same location as where they are reported by U-Boot - in their real HW offset. Link: https://lore.kernel.org/r/20220824112124.21675-1-pali@kernel.org Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
164 lines
4.1 KiB
C
164 lines
4.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __PCI_BRIDGE_EMUL_H__
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#define __PCI_BRIDGE_EMUL_H__
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#include <linux/kernel.h>
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/* PCI configuration space of a PCI-to-PCI bridge. */
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struct pci_bridge_emul_conf {
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__le16 vendor;
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__le16 device;
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__le16 command;
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__le16 status;
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__le32 class_revision;
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u8 cache_line_size;
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u8 latency_timer;
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u8 header_type;
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u8 bist;
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__le32 bar[2];
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u8 primary_bus;
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u8 secondary_bus;
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u8 subordinate_bus;
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u8 secondary_latency_timer;
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u8 iobase;
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u8 iolimit;
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__le16 secondary_status;
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__le16 membase;
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__le16 memlimit;
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__le16 pref_mem_base;
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__le16 pref_mem_limit;
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__le32 prefbaseupper;
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__le32 preflimitupper;
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__le16 iobaseupper;
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__le16 iolimitupper;
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u8 capabilities_pointer;
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u8 reserve[3];
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__le32 romaddr;
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u8 intline;
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u8 intpin;
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__le16 bridgectrl;
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};
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/* PCI configuration space of the PCIe capabilities */
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struct pci_bridge_emul_pcie_conf {
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u8 cap_id;
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u8 next;
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__le16 cap;
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__le32 devcap;
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__le16 devctl;
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__le16 devsta;
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__le32 lnkcap;
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__le16 lnkctl;
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__le16 lnksta;
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__le32 slotcap;
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__le16 slotctl;
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__le16 slotsta;
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__le16 rootctl;
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__le16 rootcap;
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__le32 rootsta;
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__le32 devcap2;
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__le16 devctl2;
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__le16 devsta2;
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__le32 lnkcap2;
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__le16 lnkctl2;
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__le16 lnksta2;
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__le32 slotcap2;
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__le16 slotctl2;
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__le16 slotsta2;
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};
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struct pci_bridge_emul;
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typedef enum { PCI_BRIDGE_EMUL_HANDLED,
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PCI_BRIDGE_EMUL_NOT_HANDLED } pci_bridge_emul_read_status_t;
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struct pci_bridge_emul_ops {
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/*
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* Called when reading from the regular PCI bridge
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* configuration space. Return PCI_BRIDGE_EMUL_HANDLED when the
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* operation has handled the read operation and filled in the
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* *value, or PCI_BRIDGE_EMUL_NOT_HANDLED when the read should
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* be emulated by the common code by reading from the
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* in-memory copy of the configuration space.
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*/
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pci_bridge_emul_read_status_t (*read_base)(struct pci_bridge_emul *bridge,
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int reg, u32 *value);
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/*
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* Same as ->read_base(), except it is for reading from the
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* PCIe capability configuration space.
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*/
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pci_bridge_emul_read_status_t (*read_pcie)(struct pci_bridge_emul *bridge,
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int reg, u32 *value);
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/*
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* Same as ->read_base(), except it is for reading from the
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* PCIe extended capability configuration space.
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*/
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pci_bridge_emul_read_status_t (*read_ext)(struct pci_bridge_emul *bridge,
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int reg, u32 *value);
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/*
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* Called when writing to the regular PCI bridge configuration
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* space. old is the current value, new is the new value being
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* written, and mask indicates which parts of the value are
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* being changed.
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*/
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void (*write_base)(struct pci_bridge_emul *bridge, int reg,
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u32 old, u32 new, u32 mask);
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/*
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* Same as ->write_base(), except it is for writing from the
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* PCIe capability configuration space.
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*/
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void (*write_pcie)(struct pci_bridge_emul *bridge, int reg,
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u32 old, u32 new, u32 mask);
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/*
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* Same as ->write_base(), except it is for writing from the
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* PCIe extended capability configuration space.
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*/
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void (*write_ext)(struct pci_bridge_emul *bridge, int reg,
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u32 old, u32 new, u32 mask);
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};
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struct pci_bridge_reg_behavior;
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struct pci_bridge_emul {
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struct pci_bridge_emul_conf conf;
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struct pci_bridge_emul_pcie_conf pcie_conf;
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const struct pci_bridge_emul_ops *ops;
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struct pci_bridge_reg_behavior *pci_regs_behavior;
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struct pci_bridge_reg_behavior *pcie_cap_regs_behavior;
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void *data;
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u8 pcie_start;
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u8 ssid_start;
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bool has_pcie;
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u16 subsystem_vendor_id;
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u16 subsystem_id;
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};
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enum {
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/*
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* PCI bridge does not support forwarding of prefetchable memory
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* requests between primary and secondary buses.
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*/
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PCI_BRIDGE_EMUL_NO_PREFMEM_FORWARD = BIT(0),
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/*
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* PCI bridge does not support forwarding of IO requests between
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* primary and secondary buses.
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*/
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PCI_BRIDGE_EMUL_NO_IO_FORWARD = BIT(1),
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};
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int pci_bridge_emul_init(struct pci_bridge_emul *bridge,
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unsigned int flags);
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void pci_bridge_emul_cleanup(struct pci_bridge_emul *bridge);
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int pci_bridge_emul_conf_read(struct pci_bridge_emul *bridge, int where,
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int size, u32 *value);
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int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where,
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int size, u32 value);
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#endif /* __PCI_BRIDGE_EMUL_H__ */
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