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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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6484be9dd1
The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230714175142.4067795-1-robh@kernel.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
335 lines
9.4 KiB
C
335 lines
9.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2011-2014, The Linux Foundation. All rights reserved.
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* Copyright (c) 2014,2015, Linaro Ltd.
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*
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* SAW power controller driver
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/of.h>
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#include <linux/err.h>
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#include <linux/platform_device.h>
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#include <soc/qcom/spm.h>
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#define SPM_CTL_INDEX 0x7f
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#define SPM_CTL_INDEX_SHIFT 4
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#define SPM_CTL_EN BIT(0)
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enum spm_reg {
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SPM_REG_CFG,
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SPM_REG_SPM_CTL,
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SPM_REG_DLY,
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SPM_REG_PMIC_DLY,
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SPM_REG_PMIC_DATA_0,
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SPM_REG_PMIC_DATA_1,
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SPM_REG_VCTL,
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SPM_REG_SEQ_ENTRY,
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SPM_REG_SPM_STS,
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SPM_REG_PMIC_STS,
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SPM_REG_AVS_CTL,
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SPM_REG_AVS_LIMIT,
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SPM_REG_NR,
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};
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static const u16 spm_reg_offset_v4_1[SPM_REG_NR] = {
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[SPM_REG_AVS_CTL] = 0x904,
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[SPM_REG_AVS_LIMIT] = 0x908,
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};
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static const struct spm_reg_data spm_reg_660_gold_l2 = {
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.reg_offset = spm_reg_offset_v4_1,
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.avs_ctl = 0x1010031,
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.avs_limit = 0x4580458,
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};
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static const struct spm_reg_data spm_reg_660_silver_l2 = {
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.reg_offset = spm_reg_offset_v4_1,
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.avs_ctl = 0x101c031,
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.avs_limit = 0x4580458,
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};
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static const struct spm_reg_data spm_reg_8998_gold_l2 = {
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.reg_offset = spm_reg_offset_v4_1,
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.avs_ctl = 0x1010031,
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.avs_limit = 0x4700470,
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};
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static const struct spm_reg_data spm_reg_8998_silver_l2 = {
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.reg_offset = spm_reg_offset_v4_1,
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.avs_ctl = 0x1010031,
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.avs_limit = 0x4200420,
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};
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static const u16 spm_reg_offset_v3_0[SPM_REG_NR] = {
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[SPM_REG_CFG] = 0x08,
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[SPM_REG_SPM_CTL] = 0x30,
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[SPM_REG_DLY] = 0x34,
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[SPM_REG_SEQ_ENTRY] = 0x400,
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};
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/* SPM register data for 8909 */
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static const struct spm_reg_data spm_reg_8909_cpu = {
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.reg_offset = spm_reg_offset_v3_0,
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.spm_cfg = 0x1,
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.spm_dly = 0x3C102800,
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.seq = { 0x60, 0x03, 0x60, 0x0B, 0x0F, 0x20, 0x10, 0x80, 0x30, 0x90,
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0x5B, 0x60, 0x03, 0x60, 0x76, 0x76, 0x0B, 0x94, 0x5B, 0x80,
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0x10, 0x26, 0x30, 0x0F },
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.start_index[PM_SLEEP_MODE_STBY] = 0,
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.start_index[PM_SLEEP_MODE_SPC] = 5,
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};
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/* SPM register data for 8916 */
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static const struct spm_reg_data spm_reg_8916_cpu = {
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.reg_offset = spm_reg_offset_v3_0,
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.spm_cfg = 0x1,
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.spm_dly = 0x3C102800,
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.seq = { 0x60, 0x03, 0x60, 0x0B, 0x0F, 0x20, 0x10, 0x80, 0x30, 0x90,
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0x5B, 0x60, 0x03, 0x60, 0x3B, 0x76, 0x76, 0x0B, 0x94, 0x5B,
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0x80, 0x10, 0x26, 0x30, 0x0F },
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.start_index[PM_SLEEP_MODE_STBY] = 0,
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.start_index[PM_SLEEP_MODE_SPC] = 5,
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};
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static const struct spm_reg_data spm_reg_8939_cpu = {
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.reg_offset = spm_reg_offset_v3_0,
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.spm_cfg = 0x1,
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.spm_dly = 0x3C102800,
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.seq = { 0x60, 0x03, 0x60, 0x0B, 0x0F, 0x20, 0x50, 0x1B, 0x10, 0x80,
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0x30, 0x90, 0x5B, 0x60, 0x50, 0x03, 0x60, 0x76, 0x76, 0x0B,
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0x50, 0x1B, 0x94, 0x5B, 0x80, 0x10, 0x26, 0x30, 0x50, 0x0F },
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.start_index[PM_SLEEP_MODE_STBY] = 0,
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.start_index[PM_SLEEP_MODE_SPC] = 5,
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};
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static const u16 spm_reg_offset_v2_3[SPM_REG_NR] = {
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[SPM_REG_CFG] = 0x08,
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[SPM_REG_SPM_CTL] = 0x30,
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[SPM_REG_DLY] = 0x34,
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[SPM_REG_PMIC_DATA_0] = 0x40,
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[SPM_REG_PMIC_DATA_1] = 0x44,
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};
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/* SPM register data for 8976 */
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static const struct spm_reg_data spm_reg_8976_gold_l2 = {
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.reg_offset = spm_reg_offset_v2_3,
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.spm_cfg = 0x14,
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.spm_dly = 0x3c11840a,
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.pmic_data[0] = 0x03030080,
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.pmic_data[1] = 0x00030000,
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.start_index[PM_SLEEP_MODE_STBY] = 0,
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.start_index[PM_SLEEP_MODE_SPC] = 3,
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};
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static const struct spm_reg_data spm_reg_8976_silver_l2 = {
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.reg_offset = spm_reg_offset_v2_3,
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.spm_cfg = 0x14,
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.spm_dly = 0x3c102800,
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.pmic_data[0] = 0x03030080,
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.pmic_data[1] = 0x00030000,
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.start_index[PM_SLEEP_MODE_STBY] = 0,
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.start_index[PM_SLEEP_MODE_SPC] = 2,
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};
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static const u16 spm_reg_offset_v2_1[SPM_REG_NR] = {
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[SPM_REG_CFG] = 0x08,
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[SPM_REG_SPM_CTL] = 0x30,
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[SPM_REG_DLY] = 0x34,
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[SPM_REG_SEQ_ENTRY] = 0x80,
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};
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/* SPM register data for 8974, 8084 */
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static const struct spm_reg_data spm_reg_8974_8084_cpu = {
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.reg_offset = spm_reg_offset_v2_1,
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.spm_cfg = 0x1,
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.spm_dly = 0x3C102800,
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.seq = { 0x03, 0x0B, 0x0F, 0x00, 0x20, 0x80, 0x10, 0xE8, 0x5B, 0x03,
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0x3B, 0xE8, 0x5B, 0x82, 0x10, 0x0B, 0x30, 0x06, 0x26, 0x30,
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0x0F },
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.start_index[PM_SLEEP_MODE_STBY] = 0,
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.start_index[PM_SLEEP_MODE_SPC] = 3,
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};
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/* SPM register data for 8226 */
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static const struct spm_reg_data spm_reg_8226_cpu = {
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.reg_offset = spm_reg_offset_v2_1,
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.spm_cfg = 0x0,
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.spm_dly = 0x3C102800,
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.seq = { 0x60, 0x03, 0x60, 0x0B, 0x0F, 0x20, 0x10, 0x80, 0x30, 0x90,
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0x5B, 0x60, 0x03, 0x60, 0x3B, 0x76, 0x76, 0x0B, 0x94, 0x5B,
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0x80, 0x10, 0x26, 0x30, 0x0F },
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.start_index[PM_SLEEP_MODE_STBY] = 0,
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.start_index[PM_SLEEP_MODE_SPC] = 5,
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};
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static const u16 spm_reg_offset_v1_1[SPM_REG_NR] = {
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[SPM_REG_CFG] = 0x08,
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[SPM_REG_SPM_CTL] = 0x20,
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[SPM_REG_PMIC_DLY] = 0x24,
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[SPM_REG_PMIC_DATA_0] = 0x28,
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[SPM_REG_PMIC_DATA_1] = 0x2C,
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[SPM_REG_SEQ_ENTRY] = 0x80,
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};
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/* SPM register data for 8064 */
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static const struct spm_reg_data spm_reg_8064_cpu = {
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.reg_offset = spm_reg_offset_v1_1,
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.spm_cfg = 0x1F,
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.pmic_dly = 0x02020004,
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.pmic_data[0] = 0x0084009C,
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.pmic_data[1] = 0x00A4001C,
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.seq = { 0x03, 0x0F, 0x00, 0x24, 0x54, 0x10, 0x09, 0x03, 0x01,
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0x10, 0x54, 0x30, 0x0C, 0x24, 0x30, 0x0F },
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.start_index[PM_SLEEP_MODE_STBY] = 0,
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.start_index[PM_SLEEP_MODE_SPC] = 2,
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};
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static inline void spm_register_write(struct spm_driver_data *drv,
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enum spm_reg reg, u32 val)
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{
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if (drv->reg_data->reg_offset[reg])
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writel_relaxed(val, drv->reg_base +
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drv->reg_data->reg_offset[reg]);
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}
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/* Ensure a guaranteed write, before return */
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static inline void spm_register_write_sync(struct spm_driver_data *drv,
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enum spm_reg reg, u32 val)
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{
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u32 ret;
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if (!drv->reg_data->reg_offset[reg])
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return;
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do {
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writel_relaxed(val, drv->reg_base +
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drv->reg_data->reg_offset[reg]);
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ret = readl_relaxed(drv->reg_base +
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drv->reg_data->reg_offset[reg]);
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if (ret == val)
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break;
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cpu_relax();
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} while (1);
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}
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static inline u32 spm_register_read(struct spm_driver_data *drv,
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enum spm_reg reg)
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{
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return readl_relaxed(drv->reg_base + drv->reg_data->reg_offset[reg]);
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}
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void spm_set_low_power_mode(struct spm_driver_data *drv,
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enum pm_sleep_mode mode)
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{
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u32 start_index;
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u32 ctl_val;
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start_index = drv->reg_data->start_index[mode];
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ctl_val = spm_register_read(drv, SPM_REG_SPM_CTL);
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ctl_val &= ~(SPM_CTL_INDEX << SPM_CTL_INDEX_SHIFT);
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ctl_val |= start_index << SPM_CTL_INDEX_SHIFT;
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ctl_val |= SPM_CTL_EN;
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spm_register_write_sync(drv, SPM_REG_SPM_CTL, ctl_val);
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}
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static const struct of_device_id spm_match_table[] = {
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{ .compatible = "qcom,sdm660-gold-saw2-v4.1-l2",
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.data = &spm_reg_660_gold_l2 },
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{ .compatible = "qcom,sdm660-silver-saw2-v4.1-l2",
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.data = &spm_reg_660_silver_l2 },
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{ .compatible = "qcom,msm8226-saw2-v2.1-cpu",
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.data = &spm_reg_8226_cpu },
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{ .compatible = "qcom,msm8909-saw2-v3.0-cpu",
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.data = &spm_reg_8909_cpu },
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{ .compatible = "qcom,msm8916-saw2-v3.0-cpu",
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.data = &spm_reg_8916_cpu },
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{ .compatible = "qcom,msm8939-saw2-v3.0-cpu",
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.data = &spm_reg_8939_cpu },
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{ .compatible = "qcom,msm8974-saw2-v2.1-cpu",
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.data = &spm_reg_8974_8084_cpu },
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{ .compatible = "qcom,msm8976-gold-saw2-v2.3-l2",
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.data = &spm_reg_8976_gold_l2 },
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{ .compatible = "qcom,msm8976-silver-saw2-v2.3-l2",
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.data = &spm_reg_8976_silver_l2 },
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{ .compatible = "qcom,msm8998-gold-saw2-v4.1-l2",
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.data = &spm_reg_8998_gold_l2 },
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{ .compatible = "qcom,msm8998-silver-saw2-v4.1-l2",
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.data = &spm_reg_8998_silver_l2 },
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{ .compatible = "qcom,apq8084-saw2-v2.1-cpu",
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.data = &spm_reg_8974_8084_cpu },
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{ .compatible = "qcom,apq8064-saw2-v1.1-cpu",
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.data = &spm_reg_8064_cpu },
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{ },
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};
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MODULE_DEVICE_TABLE(of, spm_match_table);
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static int spm_dev_probe(struct platform_device *pdev)
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{
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const struct of_device_id *match_id;
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struct spm_driver_data *drv;
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void __iomem *addr;
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drv = devm_kzalloc(&pdev->dev, sizeof(*drv), GFP_KERNEL);
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if (!drv)
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return -ENOMEM;
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drv->reg_base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(drv->reg_base))
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return PTR_ERR(drv->reg_base);
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match_id = of_match_node(spm_match_table, pdev->dev.of_node);
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if (!match_id)
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return -ENODEV;
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drv->reg_data = match_id->data;
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platform_set_drvdata(pdev, drv);
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/* Write the SPM sequences first.. */
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addr = drv->reg_base + drv->reg_data->reg_offset[SPM_REG_SEQ_ENTRY];
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__iowrite32_copy(addr, drv->reg_data->seq,
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ARRAY_SIZE(drv->reg_data->seq) / 4);
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/*
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* ..and then the control registers.
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* On some SoC if the control registers are written first and if the
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* CPU was held in reset, the reset signal could trigger the SPM state
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* machine, before the sequences are completely written.
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*/
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spm_register_write(drv, SPM_REG_AVS_CTL, drv->reg_data->avs_ctl);
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spm_register_write(drv, SPM_REG_AVS_LIMIT, drv->reg_data->avs_limit);
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spm_register_write(drv, SPM_REG_CFG, drv->reg_data->spm_cfg);
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spm_register_write(drv, SPM_REG_DLY, drv->reg_data->spm_dly);
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spm_register_write(drv, SPM_REG_PMIC_DLY, drv->reg_data->pmic_dly);
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spm_register_write(drv, SPM_REG_PMIC_DATA_0,
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drv->reg_data->pmic_data[0]);
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spm_register_write(drv, SPM_REG_PMIC_DATA_1,
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drv->reg_data->pmic_data[1]);
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/* Set up Standby as the default low power mode */
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if (drv->reg_data->reg_offset[SPM_REG_SPM_CTL])
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spm_set_low_power_mode(drv, PM_SLEEP_MODE_STBY);
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return 0;
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}
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static struct platform_driver spm_driver = {
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.probe = spm_dev_probe,
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.driver = {
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.name = "qcom_spm",
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.of_match_table = spm_match_table,
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},
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};
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static int __init qcom_spm_init(void)
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{
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return platform_driver_register(&spm_driver);
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}
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arch_initcall(qcom_spm_init);
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MODULE_LICENSE("GPL v2");
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