Sudeep Holla 1dff32d7df arm64: dts: vexpress: Support GICC_DIR operations ... The GICv2 CPU interface registers span across 8K, not 4K as indicated in the DT. Only the GICC_DIR register is located after the initial 4K boundary, leaving a functional system but without support for separately EOI'ing and deactivating interrupts. After this change the system supports split priority drop and interrupt deactivation. This patch is based on similar one from Christoffer Dall: commit 368400e242 ("ARM: dts: vexpress: Support GICC_DIR operations") Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>		2016-12-30 15:31:24 +00:00
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dts	arm64: dts: vexpress: Support GICC_DIR operations	2016-12-30 15:31:24 +00:00
.gitignore
install.sh	arm64: kbuild: make "make install" not depend on vmlinux	2016-02-19 10:33:35 +00:00
Makefile	arm64: localise Image objcopy flags	2016-07-19 15:30:23 +01:00