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8ef8f360cf
This patch adds the bare minimum required to expose the ARMv8.5 Branch Target Identification feature to userspace. By itself, this does _not_ automatically enable BTI for any initial executable pages mapped by execve(). This will come later, but for now it should be possible to enable BTI manually on those pages by using mprotect() from within the target process. Other arches already using the generic mman.h are already using 0x10 for arch-specific prot flags, so we use that for PROT_BTI here. For consistency, signal handler entry points in BTI guarded pages are required to be annotated as such, just like any other function. This blocks a relatively minor attack vector, but comforming userspace will have the annotations anyway, so we may as well enforce them. Signed-off-by: Mark Brown <broonie@kernel.org> Signed-off-by: Dave Martin <Dave.Martin@arm.com> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
333 lines
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ReStructuredText
333 lines
14 KiB
ReStructuredText
===========================
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ARM64 CPU Feature Registers
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===========================
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Author: Suzuki K Poulose <suzuki.poulose@arm.com>
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This file describes the ABI for exporting the AArch64 CPU ID/feature
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registers to userspace. The availability of this ABI is advertised
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via the HWCAP_CPUID in HWCAPs.
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1. Motivation
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-------------
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The ARM architecture defines a set of feature registers, which describe
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the capabilities of the CPU/system. Access to these system registers is
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restricted from EL0 and there is no reliable way for an application to
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extract this information to make better decisions at runtime. There is
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limited information available to the application via HWCAPs, however
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there are some issues with their usage.
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a) Any change to the HWCAPs requires an update to userspace (e.g libc)
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to detect the new changes, which can take a long time to appear in
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distributions. Exposing the registers allows applications to get the
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information without requiring updates to the toolchains.
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b) Access to HWCAPs is sometimes limited (e.g prior to libc, or
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when ld is initialised at startup time).
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c) HWCAPs cannot represent non-boolean information effectively. The
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architecture defines a canonical format for representing features
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in the ID registers; this is well defined and is capable of
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representing all valid architecture variations.
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2. Requirements
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---------------
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a) Safety:
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Applications should be able to use the information provided by the
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infrastructure to run safely across the system. This has greater
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implications on a system with heterogeneous CPUs.
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The infrastructure exports a value that is safe across all the
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available CPU on the system.
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e.g, If at least one CPU doesn't implement CRC32 instructions, while
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others do, we should report that the CRC32 is not implemented.
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Otherwise an application could crash when scheduled on the CPU
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which doesn't support CRC32.
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b) Security:
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Applications should only be able to receive information that is
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relevant to the normal operation in userspace. Hence, some of the
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fields are masked out(i.e, made invisible) and their values are set to
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indicate the feature is 'not supported'. See Section 4 for the list
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of visible features. Also, the kernel may manipulate the fields
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based on what it supports. e.g, If FP is not supported by the
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kernel, the values could indicate that the FP is not available
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(even when the CPU provides it).
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c) Implementation Defined Features
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The infrastructure doesn't expose any register which is
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IMPLEMENTATION DEFINED as per ARMv8-A Architecture.
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d) CPU Identification:
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MIDR_EL1 is exposed to help identify the processor. On a
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heterogeneous system, this could be racy (just like getcpu()). The
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process could be migrated to another CPU by the time it uses the
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register value, unless the CPU affinity is set. Hence, there is no
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guarantee that the value reflects the processor that it is
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currently executing on. The REVIDR is not exposed due to this
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constraint, as REVIDR makes sense only in conjunction with the
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MIDR. Alternately, MIDR_EL1 and REVIDR_EL1 are exposed via sysfs
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at::
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/sys/devices/system/cpu/cpu$ID/regs/identification/
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\- midr
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\- revidr
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3. Implementation
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--------------------
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The infrastructure is built on the emulation of the 'MRS' instruction.
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Accessing a restricted system register from an application generates an
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exception and ends up in SIGILL being delivered to the process.
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The infrastructure hooks into the exception handler and emulates the
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operation if the source belongs to the supported system register space.
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The infrastructure emulates only the following system register space::
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Op0=3, Op1=0, CRn=0, CRm=0,4,5,6,7
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(See Table C5-6 'System instruction encodings for non-Debug System
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register accesses' in ARMv8 ARM DDI 0487A.h, for the list of
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registers).
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The following rules are applied to the value returned by the
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infrastructure:
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a) The value of an 'IMPLEMENTATION DEFINED' field is set to 0.
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b) The value of a reserved field is populated with the reserved
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value as defined by the architecture.
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c) The value of a 'visible' field holds the system wide safe value
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for the particular feature (except for MIDR_EL1, see section 4).
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d) All other fields (i.e, invisible fields) are set to indicate
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the feature is missing (as defined by the architecture).
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4. List of registers with visible features
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-------------------------------------------
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1) ID_AA64ISAR0_EL1 - Instruction Set Attribute Register 0
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+------------------------------+---------+---------+
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| Name | bits | visible |
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+------------------------------+---------+---------+
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| RNDR | [63-60] | y |
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+------------------------------+---------+---------+
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| TS | [55-52] | y |
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+------------------------------+---------+---------+
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| FHM | [51-48] | y |
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+------------------------------+---------+---------+
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| DP | [47-44] | y |
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+------------------------------+---------+---------+
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| SM4 | [43-40] | y |
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+------------------------------+---------+---------+
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| SM3 | [39-36] | y |
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+------------------------------+---------+---------+
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| SHA3 | [35-32] | y |
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+------------------------------+---------+---------+
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| RDM | [31-28] | y |
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+------------------------------+---------+---------+
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| ATOMICS | [23-20] | y |
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+------------------------------+---------+---------+
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| CRC32 | [19-16] | y |
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+------------------------------+---------+---------+
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| SHA2 | [15-12] | y |
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+------------------------------+---------+---------+
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| SHA1 | [11-8] | y |
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+------------------------------+---------+---------+
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| AES | [7-4] | y |
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+------------------------------+---------+---------+
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2) ID_AA64PFR0_EL1 - Processor Feature Register 0
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+------------------------------+---------+---------+
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| Name | bits | visible |
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+------------------------------+---------+---------+
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| DIT | [51-48] | y |
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+------------------------------+---------+---------+
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| SVE | [35-32] | y |
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+------------------------------+---------+---------+
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| GIC | [27-24] | n |
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+------------------------------+---------+---------+
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| AdvSIMD | [23-20] | y |
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+------------------------------+---------+---------+
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| FP | [19-16] | y |
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+------------------------------+---------+---------+
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| EL3 | [15-12] | n |
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+------------------------------+---------+---------+
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| EL2 | [11-8] | n |
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+------------------------------+---------+---------+
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| EL1 | [7-4] | n |
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+------------------------------+---------+---------+
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| EL0 | [3-0] | n |
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+------------------------------+---------+---------+
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3) ID_AA64PFR1_EL1 - Processor Feature Register 1
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+------------------------------+---------+---------+
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| Name | bits | visible |
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+------------------------------+---------+---------+
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| SSBS | [7-4] | y |
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+------------------------------+---------+---------+
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| BT | [3-0] | y |
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+------------------------------+---------+---------+
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4) MIDR_EL1 - Main ID Register
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+------------------------------+---------+---------+
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| Name | bits | visible |
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+------------------------------+---------+---------+
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| Implementer | [31-24] | y |
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+------------------------------+---------+---------+
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| Variant | [23-20] | y |
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+------------------------------+---------+---------+
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| Architecture | [19-16] | y |
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+------------------------------+---------+---------+
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| PartNum | [15-4] | y |
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+------------------------------+---------+---------+
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| Revision | [3-0] | y |
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+------------------------------+---------+---------+
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NOTE: The 'visible' fields of MIDR_EL1 will contain the value
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as available on the CPU where it is fetched and is not a system
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wide safe value.
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5) ID_AA64ISAR1_EL1 - Instruction set attribute register 1
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+------------------------------+---------+---------+
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| Name | bits | visible |
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+------------------------------+---------+---------+
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| I8MM | [55-52] | y |
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+------------------------------+---------+---------+
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| DGH | [51-48] | y |
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+------------------------------+---------+---------+
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| BF16 | [47-44] | y |
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+------------------------------+---------+---------+
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| SB | [39-36] | y |
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+------------------------------+---------+---------+
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| FRINTTS | [35-32] | y |
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+------------------------------+---------+---------+
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| GPI | [31-28] | y |
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+------------------------------+---------+---------+
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| GPA | [27-24] | y |
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+------------------------------+---------+---------+
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| LRCPC | [23-20] | y |
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+------------------------------+---------+---------+
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| FCMA | [19-16] | y |
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+------------------------------+---------+---------+
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| JSCVT | [15-12] | y |
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+------------------------------+---------+---------+
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| API | [11-8] | y |
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+------------------------------+---------+---------+
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| APA | [7-4] | y |
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+------------------------------+---------+---------+
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| DPB | [3-0] | y |
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+------------------------------+---------+---------+
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6) ID_AA64MMFR2_EL1 - Memory model feature register 2
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+------------------------------+---------+---------+
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| Name | bits | visible |
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+------------------------------+---------+---------+
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| AT | [35-32] | y |
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+------------------------------+---------+---------+
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7) ID_AA64ZFR0_EL1 - SVE feature ID register 0
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+------------------------------+---------+---------+
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| Name | bits | visible |
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+------------------------------+---------+---------+
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| F64MM | [59-56] | y |
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+------------------------------+---------+---------+
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| F32MM | [55-52] | y |
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+------------------------------+---------+---------+
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| I8MM | [47-44] | y |
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+------------------------------+---------+---------+
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| SM4 | [43-40] | y |
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+------------------------------+---------+---------+
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| SHA3 | [35-32] | y |
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+------------------------------+---------+---------+
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| BF16 | [23-20] | y |
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+------------------------------+---------+---------+
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| BitPerm | [19-16] | y |
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+------------------------------+---------+---------+
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| AES | [7-4] | y |
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+------------------------------+---------+---------+
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| SVEVer | [3-0] | y |
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+------------------------------+---------+---------+
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Appendix I: Example
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-------------------
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::
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/*
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* Sample program to demonstrate the MRS emulation ABI.
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*
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* Copyright (C) 2015-2016, ARM Ltd
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*
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* Author: Suzuki K Poulose <suzuki.poulose@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <asm/hwcap.h>
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#include <stdio.h>
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#include <sys/auxv.h>
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#define get_cpu_ftr(id) ({ \
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unsigned long __val; \
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asm("mrs %0, "#id : "=r" (__val)); \
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printf("%-20s: 0x%016lx\n", #id, __val); \
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})
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int main(void)
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{
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if (!(getauxval(AT_HWCAP) & HWCAP_CPUID)) {
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fputs("CPUID registers unavailable\n", stderr);
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return 1;
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}
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get_cpu_ftr(ID_AA64ISAR0_EL1);
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get_cpu_ftr(ID_AA64ISAR1_EL1);
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get_cpu_ftr(ID_AA64MMFR0_EL1);
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get_cpu_ftr(ID_AA64MMFR1_EL1);
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get_cpu_ftr(ID_AA64PFR0_EL1);
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get_cpu_ftr(ID_AA64PFR1_EL1);
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get_cpu_ftr(ID_AA64DFR0_EL1);
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get_cpu_ftr(ID_AA64DFR1_EL1);
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get_cpu_ftr(MIDR_EL1);
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get_cpu_ftr(MPIDR_EL1);
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get_cpu_ftr(REVIDR_EL1);
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#if 0
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/* Unexposed register access causes SIGILL */
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get_cpu_ftr(ID_MMFR0_EL1);
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#endif
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return 0;
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}
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