283 lines
7.1 KiB
ArmAsm
283 lines
7.1 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020-2023 Loongson Technology Corporation Limited
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*/
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#include <linux/linkage.h>
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#include <asm/asm.h>
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#include <asm/asmmacro.h>
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#include <asm/loongarch.h>
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#include <asm/regdef.h>
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#include <asm/unwind_hints.h>
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#define HGPR_OFFSET(x) (PT_R0 + 8*x)
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#define GGPR_OFFSET(x) (KVM_ARCH_GGPR + 8*x)
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.macro kvm_save_host_gpr base
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.irp n,1,2,3,22,23,24,25,26,27,28,29,30,31
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st.d $r\n, \base, HGPR_OFFSET(\n)
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.endr
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.endm
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.macro kvm_restore_host_gpr base
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.irp n,1,2,3,22,23,24,25,26,27,28,29,30,31
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ld.d $r\n, \base, HGPR_OFFSET(\n)
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.endr
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.endm
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/*
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* Save and restore all GPRs except base register,
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* and default value of base register is a2.
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*/
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.macro kvm_save_guest_gprs base
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.irp n,1,2,3,4,5,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
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st.d $r\n, \base, GGPR_OFFSET(\n)
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.endr
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.endm
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.macro kvm_restore_guest_gprs base
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.irp n,1,2,3,4,5,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
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ld.d $r\n, \base, GGPR_OFFSET(\n)
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.endr
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.endm
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/*
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* Prepare switch to guest, save host regs and restore guest regs.
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* a2: kvm_vcpu_arch, don't touch it until 'ertn'
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* t0, t1: temp register
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*/
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.macro kvm_switch_to_guest
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/* Set host ECFG.VS=0, all exceptions share one exception entry */
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csrrd t0, LOONGARCH_CSR_ECFG
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bstrins.w t0, zero, CSR_ECFG_VS_SHIFT_END, CSR_ECFG_VS_SHIFT
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csrwr t0, LOONGARCH_CSR_ECFG
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/* Load up the new EENTRY */
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ld.d t0, a2, KVM_ARCH_GEENTRY
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csrwr t0, LOONGARCH_CSR_EENTRY
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/* Set Guest ERA */
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ld.d t0, a2, KVM_ARCH_GPC
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csrwr t0, LOONGARCH_CSR_ERA
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/* Save host PGDL */
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csrrd t0, LOONGARCH_CSR_PGDL
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st.d t0, a2, KVM_ARCH_HPGD
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/* Switch to kvm */
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ld.d t1, a2, KVM_VCPU_KVM - KVM_VCPU_ARCH
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/* Load guest PGDL */
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li.w t0, KVM_GPGD
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ldx.d t0, t1, t0
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csrwr t0, LOONGARCH_CSR_PGDL
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/* Mix GID and RID */
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csrrd t1, LOONGARCH_CSR_GSTAT
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bstrpick.w t1, t1, CSR_GSTAT_GID_SHIFT_END, CSR_GSTAT_GID_SHIFT
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csrrd t0, LOONGARCH_CSR_GTLBC
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bstrins.w t0, t1, CSR_GTLBC_TGID_SHIFT_END, CSR_GTLBC_TGID_SHIFT
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csrwr t0, LOONGARCH_CSR_GTLBC
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/*
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* Enable intr in root mode with future ertn so that host interrupt
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* can be responsed during VM runs
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* Guest CRMD comes from separate GCSR_CRMD register
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*/
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ori t0, zero, CSR_PRMD_PIE
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csrxchg t0, t0, LOONGARCH_CSR_PRMD
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/* Set PVM bit to setup ertn to guest context */
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ori t0, zero, CSR_GSTAT_PVM
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csrxchg t0, t0, LOONGARCH_CSR_GSTAT
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/* Load Guest GPRs */
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kvm_restore_guest_gprs a2
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/* Load KVM_ARCH register */
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ld.d a2, a2, (KVM_ARCH_GGPR + 8 * REG_A2)
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ertn /* Switch to guest: GSTAT.PGM = 1, ERRCTL.ISERR = 0, TLBRPRMD.ISTLBR = 0 */
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.endm
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/*
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* Exception entry for general exception from guest mode
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* - IRQ is disabled
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* - kernel privilege in root mode
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* - page mode keep unchanged from previous PRMD in root mode
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* - Fixme: tlb exception cannot happen since registers relative with TLB
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* - is still in guest mode, such as pgd table/vmid registers etc,
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* - will fix with hw page walk enabled in future
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* load kvm_vcpu from reserved CSR KVM_VCPU_KS, and save a2 to KVM_TEMP_KS
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*/
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.text
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.cfi_sections .debug_frame
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SYM_CODE_START(kvm_exc_entry)
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UNWIND_HINT_UNDEFINED
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csrwr a2, KVM_TEMP_KS
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csrrd a2, KVM_VCPU_KS
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addi.d a2, a2, KVM_VCPU_ARCH
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/* After save GPRs, free to use any GPR */
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kvm_save_guest_gprs a2
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/* Save guest A2 */
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csrrd t0, KVM_TEMP_KS
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st.d t0, a2, (KVM_ARCH_GGPR + 8 * REG_A2)
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/* A2 is kvm_vcpu_arch, A1 is free to use */
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csrrd s1, KVM_VCPU_KS
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ld.d s0, s1, KVM_VCPU_RUN
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csrrd t0, LOONGARCH_CSR_ESTAT
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st.d t0, a2, KVM_ARCH_HESTAT
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csrrd t0, LOONGARCH_CSR_ERA
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st.d t0, a2, KVM_ARCH_GPC
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csrrd t0, LOONGARCH_CSR_BADV
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st.d t0, a2, KVM_ARCH_HBADV
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csrrd t0, LOONGARCH_CSR_BADI
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st.d t0, a2, KVM_ARCH_HBADI
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/* Restore host ECFG.VS */
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csrrd t0, LOONGARCH_CSR_ECFG
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ld.d t1, a2, KVM_ARCH_HECFG
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or t0, t0, t1
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csrwr t0, LOONGARCH_CSR_ECFG
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/* Restore host EENTRY */
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ld.d t0, a2, KVM_ARCH_HEENTRY
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csrwr t0, LOONGARCH_CSR_EENTRY
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/* Restore host pgd table */
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ld.d t0, a2, KVM_ARCH_HPGD
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csrwr t0, LOONGARCH_CSR_PGDL
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/*
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* Disable PGM bit to enter root mode by default with next ertn
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*/
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ori t0, zero, CSR_GSTAT_PVM
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csrxchg zero, t0, LOONGARCH_CSR_GSTAT
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/*
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* Clear GTLBC.TGID field
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* 0: for root tlb update in future tlb instr
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* others: for guest tlb update like gpa to hpa in future tlb instr
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*/
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csrrd t0, LOONGARCH_CSR_GTLBC
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bstrins.w t0, zero, CSR_GTLBC_TGID_SHIFT_END, CSR_GTLBC_TGID_SHIFT
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csrwr t0, LOONGARCH_CSR_GTLBC
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ld.d tp, a2, KVM_ARCH_HTP
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ld.d sp, a2, KVM_ARCH_HSP
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/* restore per cpu register */
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ld.d u0, a2, KVM_ARCH_HPERCPU
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addi.d sp, sp, -PT_SIZE
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/* Prepare handle exception */
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or a0, s0, zero
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or a1, s1, zero
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ld.d t8, a2, KVM_ARCH_HANDLE_EXIT
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jirl ra, t8, 0
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or a2, s1, zero
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addi.d a2, a2, KVM_VCPU_ARCH
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/* Resume host when ret <= 0 */
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blez a0, ret_to_host
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/*
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* Return to guest
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* Save per cpu register again, maybe switched to another cpu
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*/
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st.d u0, a2, KVM_ARCH_HPERCPU
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/* Save kvm_vcpu to kscratch */
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csrwr s1, KVM_VCPU_KS
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kvm_switch_to_guest
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ret_to_host:
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ld.d a2, a2, KVM_ARCH_HSP
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addi.d a2, a2, -PT_SIZE
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kvm_restore_host_gpr a2
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jr ra
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SYM_INNER_LABEL(kvm_exc_entry_end, SYM_L_LOCAL)
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SYM_CODE_END(kvm_exc_entry)
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/*
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* int kvm_enter_guest(struct kvm_run *run, struct kvm_vcpu *vcpu)
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*
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* @register_param:
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* a0: kvm_run* run
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* a1: kvm_vcpu* vcpu
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*/
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SYM_FUNC_START(kvm_enter_guest)
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/* Allocate space in stack bottom */
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addi.d a2, sp, -PT_SIZE
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/* Save host GPRs */
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kvm_save_host_gpr a2
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addi.d a2, a1, KVM_VCPU_ARCH
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st.d sp, a2, KVM_ARCH_HSP
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st.d tp, a2, KVM_ARCH_HTP
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/* Save per cpu register */
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st.d u0, a2, KVM_ARCH_HPERCPU
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/* Save kvm_vcpu to kscratch */
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csrwr a1, KVM_VCPU_KS
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kvm_switch_to_guest
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SYM_INNER_LABEL(kvm_enter_guest_end, SYM_L_LOCAL)
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SYM_FUNC_END(kvm_enter_guest)
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SYM_FUNC_START(kvm_save_fpu)
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fpu_save_csr a0 t1
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fpu_save_double a0 t1
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fpu_save_cc a0 t1 t2
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jr ra
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SYM_FUNC_END(kvm_save_fpu)
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SYM_FUNC_START(kvm_restore_fpu)
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fpu_restore_double a0 t1
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fpu_restore_csr a0 t1 t2
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fpu_restore_cc a0 t1 t2
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jr ra
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SYM_FUNC_END(kvm_restore_fpu)
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#ifdef CONFIG_CPU_HAS_LSX
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SYM_FUNC_START(kvm_save_lsx)
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fpu_save_csr a0 t1
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fpu_save_cc a0 t1 t2
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lsx_save_data a0 t1
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jr ra
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SYM_FUNC_END(kvm_save_lsx)
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SYM_FUNC_START(kvm_restore_lsx)
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lsx_restore_data a0 t1
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fpu_restore_cc a0 t1 t2
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fpu_restore_csr a0 t1 t2
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jr ra
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SYM_FUNC_END(kvm_restore_lsx)
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#endif
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#ifdef CONFIG_CPU_HAS_LASX
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SYM_FUNC_START(kvm_save_lasx)
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fpu_save_csr a0 t1
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fpu_save_cc a0 t1 t2
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lasx_save_data a0 t1
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jr ra
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SYM_FUNC_END(kvm_save_lasx)
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SYM_FUNC_START(kvm_restore_lasx)
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lasx_restore_data a0 t1
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fpu_restore_cc a0 t1 t2
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fpu_restore_csr a0 t1 t2
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jr ra
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SYM_FUNC_END(kvm_restore_lasx)
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#endif
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.section ".rodata"
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SYM_DATA(kvm_exception_size, .quad kvm_exc_entry_end - kvm_exc_entry)
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SYM_DATA(kvm_enter_guest_size, .quad kvm_enter_guest_end - kvm_enter_guest)
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#ifdef CONFIG_CPU_HAS_LBT
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STACK_FRAME_NON_STANDARD kvm_restore_fpu
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STACK_FRAME_NON_STANDARD kvm_restore_lsx
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STACK_FRAME_NON_STANDARD kvm_restore_lasx
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#endif
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