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1e3dc1d862
GSC is a graphics system controller, it provides a chassis controller for graphics discrete cards. There are two MEI interfaces in GSC: HECI1 and HECI2. Both interfaces are on the BAR0 at offsets 0x00258000 and 0x00259000. GSC is a GT Engine (class 4: instance 6). HECI1 interrupt is signaled via bit 15 and HECI2 via bit 14 in the interrupt register. This patch exports GSC as auxiliary device for mei driver to bind to for HECI2 interface and prepares for HECI1 interface as it will follow up soon. CC: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com> Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com> Acked-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220419193314.526966-2-daniele.ceraolospurio@intel.com
19 lines
434 B
C
19 lines
434 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2022, Intel Corporation. All rights reserved.
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*/
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#ifndef _LINUX_MEI_AUX_H
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#define _LINUX_MEI_AUX_H
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#include <linux/auxiliary_bus.h>
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struct mei_aux_device {
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struct auxiliary_device aux_dev;
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int irq;
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struct resource bar;
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};
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#define auxiliary_dev_to_mei_aux_dev(auxiliary_dev) \
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container_of(auxiliary_dev, struct mei_aux_device, aux_dev)
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#endif /* _LINUX_MEI_AUX_H */
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