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![Kunihiko Hayashi](/assets/img/avatar_default.png)
Add an extra argument to ahci_platform_get_resources(), that is for the bitmap representing the resource to get in this function. Currently there is no resources to be defined, so all the callers set '0' to the argument. Suggested-by: Hans de Goede <hdegoede@redhat.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Matthias Brugger <matthias.bgg@gmail.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Tejun Heo <tj@kernel.org>
596 lines
18 KiB
C
596 lines
18 KiB
C
/*
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* drivers/ata/ahci_tegra.c
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*
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* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
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*
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* Author:
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* Mikko Perttunen <mperttunen@nvidia.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/ahci_platform.h>
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#include <linux/errno.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/regulator/consumer.h>
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#include <linux/reset.h>
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#include <soc/tegra/fuse.h>
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#include <soc/tegra/pmc.h>
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#include "ahci.h"
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#define DRV_NAME "tegra-ahci"
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#define SATA_CONFIGURATION_0 0x180
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#define SATA_CONFIGURATION_0_EN_FPCI BIT(0)
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#define SATA_CONFIGURATION_0_CLK_OVERRIDE BIT(31)
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#define SCFG_OFFSET 0x1000
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#define T_SATA0_CFG_1 0x04
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#define T_SATA0_CFG_1_IO_SPACE BIT(0)
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#define T_SATA0_CFG_1_MEMORY_SPACE BIT(1)
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#define T_SATA0_CFG_1_BUS_MASTER BIT(2)
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#define T_SATA0_CFG_1_SERR BIT(8)
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#define T_SATA0_CFG_9 0x24
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#define T_SATA0_CFG_9_BASE_ADDRESS 0x40020000
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#define SATA_FPCI_BAR5 0x94
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#define SATA_FPCI_BAR5_START_MASK (0xfffffff << 4)
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#define SATA_FPCI_BAR5_START (0x0040020 << 4)
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#define SATA_FPCI_BAR5_ACCESS_TYPE (0x1)
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#define SATA_INTR_MASK 0x188
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#define SATA_INTR_MASK_IP_INT_MASK BIT(16)
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#define T_SATA0_CFG_35 0x94
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#define T_SATA0_CFG_35_IDP_INDEX_MASK (0x7ff << 2)
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#define T_SATA0_CFG_35_IDP_INDEX (0x2a << 2)
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#define T_SATA0_AHCI_IDP1 0x98
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#define T_SATA0_AHCI_IDP1_DATA (0x400040)
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#define T_SATA0_CFG_PHY_1 0x12c
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#define T_SATA0_CFG_PHY_1_PADS_IDDQ_EN BIT(23)
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#define T_SATA0_CFG_PHY_1_PAD_PLL_IDDQ_EN BIT(22)
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#define T_SATA0_NVOOB 0x114
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#define T_SATA0_NVOOB_COMMA_CNT_MASK (0xff << 16)
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#define T_SATA0_NVOOB_COMMA_CNT (0x07 << 16)
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#define T_SATA0_NVOOB_SQUELCH_FILTER_MODE_MASK (0x3 << 24)
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#define T_SATA0_NVOOB_SQUELCH_FILTER_MODE (0x1 << 24)
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#define T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH_MASK (0x3 << 26)
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#define T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH (0x3 << 26)
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#define T_SATA_CFG_PHY_0 0x120
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#define T_SATA_CFG_PHY_0_USE_7BIT_ALIGN_DET_FOR_SPD BIT(11)
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#define T_SATA_CFG_PHY_0_MASK_SQUELCH BIT(24)
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#define T_SATA0_CFG2NVOOB_2 0x134
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#define T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW_MASK (0x1ff << 18)
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#define T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW (0xc << 18)
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#define T_SATA0_AHCI_HBA_CAP_BKDR 0x300
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#define T_SATA0_AHCI_HBA_CAP_BKDR_PARTIAL_ST_CAP BIT(13)
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#define T_SATA0_AHCI_HBA_CAP_BKDR_SLUMBER_ST_CAP BIT(14)
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#define T_SATA0_AHCI_HBA_CAP_BKDR_SALP BIT(26)
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#define T_SATA0_AHCI_HBA_CAP_BKDR_SUPP_PM BIT(17)
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#define T_SATA0_AHCI_HBA_CAP_BKDR_SNCQ BIT(30)
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#define T_SATA0_BKDOOR_CC 0x4a4
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#define T_SATA0_BKDOOR_CC_CLASS_CODE_MASK (0xffff << 16)
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#define T_SATA0_BKDOOR_CC_CLASS_CODE (0x0106 << 16)
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#define T_SATA0_BKDOOR_CC_PROG_IF_MASK (0xff << 8)
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#define T_SATA0_BKDOOR_CC_PROG_IF (0x01 << 8)
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#define T_SATA0_CFG_SATA 0x54c
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#define T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN BIT(12)
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#define T_SATA0_CFG_MISC 0x550
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#define T_SATA0_INDEX 0x680
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#define T_SATA0_CHX_PHY_CTRL1_GEN1 0x690
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#define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK 0xff
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#define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT 0
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#define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK (0xff << 8)
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#define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT 8
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#define T_SATA0_CHX_PHY_CTRL1_GEN2 0x694
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#define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK 0xff
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#define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_SHIFT 0
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#define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK (0xff << 12)
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#define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_SHIFT 12
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#define T_SATA0_CHX_PHY_CTRL2 0x69c
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#define T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1 0x23
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#define T_SATA0_CHX_PHY_CTRL11 0x6d0
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#define T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ (0x2800 << 16)
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#define T_SATA0_CHX_PHY_CTRL17_0 0x6e8
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#define T_SATA0_CHX_PHY_CTRL17_0_RX_EQ_CTRL_L_GEN1 0x55010000
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#define T_SATA0_CHX_PHY_CTRL18_0 0x6ec
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#define T_SATA0_CHX_PHY_CTRL18_0_RX_EQ_CTRL_L_GEN2 0x55010000
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#define T_SATA0_CHX_PHY_CTRL20_0 0x6f4
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#define T_SATA0_CHX_PHY_CTRL20_0_RX_EQ_CTRL_H_GEN1 0x1
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#define T_SATA0_CHX_PHY_CTRL21_0 0x6f8
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#define T_SATA0_CHX_PHY_CTRL21_0_RX_EQ_CTRL_H_GEN2 0x1
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/* AUX Registers */
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#define SATA_AUX_MISC_CNTL_1_0 0x8
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#define SATA_AUX_MISC_CNTL_1_0_DEVSLP_OVERRIDE BIT(17)
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#define SATA_AUX_MISC_CNTL_1_0_SDS_SUPPORT BIT(13)
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#define SATA_AUX_MISC_CNTL_1_0_DESO_SUPPORT BIT(15)
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#define SATA_AUX_RX_STAT_INT_0 0xc
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#define SATA_AUX_RX_STAT_INT_0_SATA_DEVSLP BIT(7)
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#define SATA_AUX_SPARE_CFG0_0 0x18
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#define SATA_AUX_SPARE_CFG0_0_MDAT_TIMER_AFTER_PG_VALID BIT(14)
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#define FUSE_SATA_CALIB 0x124
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#define FUSE_SATA_CALIB_MASK 0x3
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struct sata_pad_calibration {
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u8 gen1_tx_amp;
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u8 gen1_tx_peak;
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u8 gen2_tx_amp;
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u8 gen2_tx_peak;
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};
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static const struct sata_pad_calibration tegra124_pad_calibration[] = {
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{0x18, 0x04, 0x18, 0x0a},
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{0x0e, 0x04, 0x14, 0x0a},
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{0x0e, 0x07, 0x1a, 0x0e},
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{0x14, 0x0e, 0x1a, 0x0e},
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};
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struct tegra_ahci_ops {
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int (*init)(struct ahci_host_priv *hpriv);
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};
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struct tegra_ahci_soc {
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const char *const *supply_names;
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u32 num_supplies;
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bool supports_devslp;
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const struct tegra_ahci_ops *ops;
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};
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struct tegra_ahci_priv {
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struct platform_device *pdev;
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void __iomem *sata_regs;
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void __iomem *sata_aux_regs;
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struct reset_control *sata_rst;
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struct reset_control *sata_oob_rst;
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struct reset_control *sata_cold_rst;
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/* Needs special handling, cannot use ahci_platform */
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struct clk *sata_clk;
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struct regulator_bulk_data *supplies;
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const struct tegra_ahci_soc *soc;
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};
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static void tegra_ahci_handle_quirks(struct ahci_host_priv *hpriv)
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{
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struct tegra_ahci_priv *tegra = hpriv->plat_data;
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u32 val;
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if (tegra->sata_aux_regs && !tegra->soc->supports_devslp) {
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val = readl(tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0);
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val &= ~SATA_AUX_MISC_CNTL_1_0_SDS_SUPPORT;
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writel(val, tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0);
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}
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}
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static int tegra124_ahci_init(struct ahci_host_priv *hpriv)
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{
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struct tegra_ahci_priv *tegra = hpriv->plat_data;
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struct sata_pad_calibration calib;
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int ret;
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u32 val;
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/* Pad calibration */
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ret = tegra_fuse_readl(FUSE_SATA_CALIB, &val);
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if (ret)
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return ret;
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calib = tegra124_pad_calibration[val & FUSE_SATA_CALIB_MASK];
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writel(BIT(0), tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX);
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val = readl(tegra->sata_regs +
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SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN1);
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val &= ~T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK;
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val &= ~T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK;
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val |= calib.gen1_tx_amp << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT;
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val |= calib.gen1_tx_peak << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT;
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writel(val, tegra->sata_regs + SCFG_OFFSET +
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T_SATA0_CHX_PHY_CTRL1_GEN1);
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val = readl(tegra->sata_regs +
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SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN2);
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val &= ~T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK;
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val &= ~T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK;
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val |= calib.gen2_tx_amp << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT;
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val |= calib.gen2_tx_peak << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT;
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writel(val, tegra->sata_regs + SCFG_OFFSET +
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T_SATA0_CHX_PHY_CTRL1_GEN2);
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writel(T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ,
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tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL11);
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writel(T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1,
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tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL2);
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writel(0, tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX);
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return 0;
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}
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static int tegra_ahci_power_on(struct ahci_host_priv *hpriv)
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{
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struct tegra_ahci_priv *tegra = hpriv->plat_data;
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int ret;
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ret = regulator_bulk_enable(tegra->soc->num_supplies,
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tegra->supplies);
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if (ret)
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return ret;
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ret = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_SATA,
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tegra->sata_clk,
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tegra->sata_rst);
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if (ret)
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goto disable_regulators;
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reset_control_assert(tegra->sata_oob_rst);
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reset_control_assert(tegra->sata_cold_rst);
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ret = ahci_platform_enable_resources(hpriv);
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if (ret)
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goto disable_power;
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reset_control_deassert(tegra->sata_cold_rst);
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reset_control_deassert(tegra->sata_oob_rst);
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return 0;
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disable_power:
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clk_disable_unprepare(tegra->sata_clk);
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tegra_powergate_power_off(TEGRA_POWERGATE_SATA);
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disable_regulators:
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regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies);
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return ret;
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}
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static void tegra_ahci_power_off(struct ahci_host_priv *hpriv)
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{
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struct tegra_ahci_priv *tegra = hpriv->plat_data;
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ahci_platform_disable_resources(hpriv);
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reset_control_assert(tegra->sata_rst);
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reset_control_assert(tegra->sata_oob_rst);
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reset_control_assert(tegra->sata_cold_rst);
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clk_disable_unprepare(tegra->sata_clk);
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tegra_powergate_power_off(TEGRA_POWERGATE_SATA);
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regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies);
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}
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static int tegra_ahci_controller_init(struct ahci_host_priv *hpriv)
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{
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struct tegra_ahci_priv *tegra = hpriv->plat_data;
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int ret;
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u32 val;
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ret = tegra_ahci_power_on(hpriv);
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if (ret) {
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dev_err(&tegra->pdev->dev,
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"failed to power on AHCI controller: %d\n", ret);
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return ret;
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}
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/*
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* Program the following SATA IPFS registers to allow SW accesses to
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* SATA's MMIO register range.
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*/
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val = readl(tegra->sata_regs + SATA_FPCI_BAR5);
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val &= ~(SATA_FPCI_BAR5_START_MASK | SATA_FPCI_BAR5_ACCESS_TYPE);
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val |= SATA_FPCI_BAR5_START | SATA_FPCI_BAR5_ACCESS_TYPE;
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writel(val, tegra->sata_regs + SATA_FPCI_BAR5);
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/* Program the following SATA IPFS register to enable the SATA */
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val = readl(tegra->sata_regs + SATA_CONFIGURATION_0);
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val |= SATA_CONFIGURATION_0_EN_FPCI;
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writel(val, tegra->sata_regs + SATA_CONFIGURATION_0);
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/* Electrical settings for better link stability */
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val = T_SATA0_CHX_PHY_CTRL17_0_RX_EQ_CTRL_L_GEN1;
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writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL17_0);
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val = T_SATA0_CHX_PHY_CTRL18_0_RX_EQ_CTRL_L_GEN2;
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writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL18_0);
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val = T_SATA0_CHX_PHY_CTRL20_0_RX_EQ_CTRL_H_GEN1;
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writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL20_0);
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val = T_SATA0_CHX_PHY_CTRL21_0_RX_EQ_CTRL_H_GEN2;
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writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL21_0);
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/* For SQUELCH Filter & Gen3 drive getting detected as Gen1 drive */
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val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA_CFG_PHY_0);
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val |= T_SATA_CFG_PHY_0_MASK_SQUELCH;
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val &= ~T_SATA_CFG_PHY_0_USE_7BIT_ALIGN_DET_FOR_SPD;
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writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA_CFG_PHY_0);
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val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_NVOOB);
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val &= ~(T_SATA0_NVOOB_COMMA_CNT_MASK |
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T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH_MASK |
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T_SATA0_NVOOB_SQUELCH_FILTER_MODE_MASK);
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val |= (T_SATA0_NVOOB_COMMA_CNT |
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T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH |
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T_SATA0_NVOOB_SQUELCH_FILTER_MODE);
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writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_NVOOB);
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/*
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* Change CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW from 83.3 ns to 58.8ns
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*/
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val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG2NVOOB_2);
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val &= ~T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW_MASK;
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val |= T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW;
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writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG2NVOOB_2);
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if (tegra->soc->ops && tegra->soc->ops->init)
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tegra->soc->ops->init(hpriv);
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/*
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* Program the following SATA configuration registers to
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* initialize SATA
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*/
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val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);
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val |= (T_SATA0_CFG_1_IO_SPACE | T_SATA0_CFG_1_MEMORY_SPACE |
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T_SATA0_CFG_1_BUS_MASTER | T_SATA0_CFG_1_SERR);
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writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);
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val = T_SATA0_CFG_9_BASE_ADDRESS;
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writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_9);
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|
/* Program Class Code and Programming interface for SATA */
|
|
val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
|
|
val |= T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN;
|
|
writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
|
|
|
|
val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_BKDOOR_CC);
|
|
val &=
|
|
~(T_SATA0_BKDOOR_CC_CLASS_CODE_MASK |
|
|
T_SATA0_BKDOOR_CC_PROG_IF_MASK);
|
|
val |= T_SATA0_BKDOOR_CC_CLASS_CODE | T_SATA0_BKDOOR_CC_PROG_IF;
|
|
writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_BKDOOR_CC);
|
|
|
|
val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
|
|
val &= ~T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN;
|
|
writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
|
|
|
|
/* Enabling LPM capabilities through Backdoor Programming */
|
|
val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_AHCI_HBA_CAP_BKDR);
|
|
val |= (T_SATA0_AHCI_HBA_CAP_BKDR_PARTIAL_ST_CAP |
|
|
T_SATA0_AHCI_HBA_CAP_BKDR_SLUMBER_ST_CAP |
|
|
T_SATA0_AHCI_HBA_CAP_BKDR_SALP |
|
|
T_SATA0_AHCI_HBA_CAP_BKDR_SUPP_PM);
|
|
writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_AHCI_HBA_CAP_BKDR);
|
|
|
|
/* SATA Second Level Clock Gating configuration
|
|
* Enabling Gating of Tx/Rx clocks and driving Pad IDDQ and Lane
|
|
* IDDQ Signals
|
|
*/
|
|
val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_35);
|
|
val &= ~T_SATA0_CFG_35_IDP_INDEX_MASK;
|
|
val |= T_SATA0_CFG_35_IDP_INDEX;
|
|
writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_35);
|
|
|
|
val = T_SATA0_AHCI_IDP1_DATA;
|
|
writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_AHCI_IDP1);
|
|
|
|
val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_PHY_1);
|
|
val |= (T_SATA0_CFG_PHY_1_PADS_IDDQ_EN |
|
|
T_SATA0_CFG_PHY_1_PAD_PLL_IDDQ_EN);
|
|
writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_PHY_1);
|
|
|
|
/* Enabling IPFS Clock Gating */
|
|
val = readl(tegra->sata_regs + SATA_CONFIGURATION_0);
|
|
val &= ~SATA_CONFIGURATION_0_CLK_OVERRIDE;
|
|
writel(val, tegra->sata_regs + SATA_CONFIGURATION_0);
|
|
|
|
tegra_ahci_handle_quirks(hpriv);
|
|
|
|
/* Unmask SATA interrupts */
|
|
|
|
val = readl(tegra->sata_regs + SATA_INTR_MASK);
|
|
val |= SATA_INTR_MASK_IP_INT_MASK;
|
|
writel(val, tegra->sata_regs + SATA_INTR_MASK);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void tegra_ahci_controller_deinit(struct ahci_host_priv *hpriv)
|
|
{
|
|
tegra_ahci_power_off(hpriv);
|
|
}
|
|
|
|
static void tegra_ahci_host_stop(struct ata_host *host)
|
|
{
|
|
struct ahci_host_priv *hpriv = host->private_data;
|
|
|
|
tegra_ahci_controller_deinit(hpriv);
|
|
}
|
|
|
|
static struct ata_port_operations ahci_tegra_port_ops = {
|
|
.inherits = &ahci_ops,
|
|
.host_stop = tegra_ahci_host_stop,
|
|
};
|
|
|
|
static const struct ata_port_info ahci_tegra_port_info = {
|
|
.flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
|
|
.pio_mask = ATA_PIO4,
|
|
.udma_mask = ATA_UDMA6,
|
|
.port_ops = &ahci_tegra_port_ops,
|
|
};
|
|
|
|
static const char *const tegra124_supply_names[] = {
|
|
"avdd", "hvdd", "vddio", "target-5v", "target-12v"
|
|
};
|
|
|
|
static const struct tegra_ahci_ops tegra124_ahci_ops = {
|
|
.init = tegra124_ahci_init,
|
|
};
|
|
|
|
static const struct tegra_ahci_soc tegra124_ahci_soc = {
|
|
.supply_names = tegra124_supply_names,
|
|
.num_supplies = ARRAY_SIZE(tegra124_supply_names),
|
|
.supports_devslp = false,
|
|
.ops = &tegra124_ahci_ops,
|
|
};
|
|
|
|
static const struct tegra_ahci_soc tegra210_ahci_soc = {
|
|
.supports_devslp = false,
|
|
};
|
|
|
|
static const struct of_device_id tegra_ahci_of_match[] = {
|
|
{
|
|
.compatible = "nvidia,tegra124-ahci",
|
|
.data = &tegra124_ahci_soc
|
|
},
|
|
{
|
|
.compatible = "nvidia,tegra210-ahci",
|
|
.data = &tegra210_ahci_soc
|
|
},
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(of, tegra_ahci_of_match);
|
|
|
|
static struct scsi_host_template ahci_platform_sht = {
|
|
AHCI_SHT(DRV_NAME),
|
|
};
|
|
|
|
static int tegra_ahci_probe(struct platform_device *pdev)
|
|
{
|
|
struct ahci_host_priv *hpriv;
|
|
struct tegra_ahci_priv *tegra;
|
|
struct resource *res;
|
|
int ret;
|
|
unsigned int i;
|
|
|
|
hpriv = ahci_platform_get_resources(pdev, 0);
|
|
if (IS_ERR(hpriv))
|
|
return PTR_ERR(hpriv);
|
|
|
|
tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
|
|
if (!tegra)
|
|
return -ENOMEM;
|
|
|
|
hpriv->plat_data = tegra;
|
|
|
|
tegra->pdev = pdev;
|
|
tegra->soc = of_device_get_match_data(&pdev->dev);
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
|
tegra->sata_regs = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(tegra->sata_regs))
|
|
return PTR_ERR(tegra->sata_regs);
|
|
|
|
/*
|
|
* AUX registers is optional.
|
|
*/
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
|
|
if (res) {
|
|
tegra->sata_aux_regs = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(tegra->sata_aux_regs))
|
|
return PTR_ERR(tegra->sata_aux_regs);
|
|
}
|
|
|
|
tegra->sata_rst = devm_reset_control_get(&pdev->dev, "sata");
|
|
if (IS_ERR(tegra->sata_rst)) {
|
|
dev_err(&pdev->dev, "Failed to get sata reset\n");
|
|
return PTR_ERR(tegra->sata_rst);
|
|
}
|
|
|
|
tegra->sata_oob_rst = devm_reset_control_get(&pdev->dev, "sata-oob");
|
|
if (IS_ERR(tegra->sata_oob_rst)) {
|
|
dev_err(&pdev->dev, "Failed to get sata-oob reset\n");
|
|
return PTR_ERR(tegra->sata_oob_rst);
|
|
}
|
|
|
|
tegra->sata_cold_rst = devm_reset_control_get(&pdev->dev, "sata-cold");
|
|
if (IS_ERR(tegra->sata_cold_rst)) {
|
|
dev_err(&pdev->dev, "Failed to get sata-cold reset\n");
|
|
return PTR_ERR(tegra->sata_cold_rst);
|
|
}
|
|
|
|
tegra->sata_clk = devm_clk_get(&pdev->dev, "sata");
|
|
if (IS_ERR(tegra->sata_clk)) {
|
|
dev_err(&pdev->dev, "Failed to get sata clock\n");
|
|
return PTR_ERR(tegra->sata_clk);
|
|
}
|
|
|
|
tegra->supplies = devm_kcalloc(&pdev->dev,
|
|
tegra->soc->num_supplies,
|
|
sizeof(*tegra->supplies), GFP_KERNEL);
|
|
if (!tegra->supplies)
|
|
return -ENOMEM;
|
|
|
|
for (i = 0; i < tegra->soc->num_supplies; i++)
|
|
tegra->supplies[i].supply = tegra->soc->supply_names[i];
|
|
|
|
ret = devm_regulator_bulk_get(&pdev->dev,
|
|
tegra->soc->num_supplies,
|
|
tegra->supplies);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Failed to get regulators\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = tegra_ahci_controller_init(hpriv);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = ahci_platform_init_host(pdev, hpriv, &ahci_tegra_port_info,
|
|
&ahci_platform_sht);
|
|
if (ret)
|
|
goto deinit_controller;
|
|
|
|
return 0;
|
|
|
|
deinit_controller:
|
|
tegra_ahci_controller_deinit(hpriv);
|
|
|
|
return ret;
|
|
};
|
|
|
|
static struct platform_driver tegra_ahci_driver = {
|
|
.probe = tegra_ahci_probe,
|
|
.remove = ata_platform_remove_one,
|
|
.driver = {
|
|
.name = DRV_NAME,
|
|
.of_match_table = tegra_ahci_of_match,
|
|
},
|
|
/* LP0 suspend support not implemented */
|
|
};
|
|
module_platform_driver(tegra_ahci_driver);
|
|
|
|
MODULE_AUTHOR("Mikko Perttunen <mperttunen@nvidia.com>");
|
|
MODULE_DESCRIPTION("Tegra AHCI SATA driver");
|
|
MODULE_LICENSE("GPL v2");
|