mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-21 16:29:59 +00:00
![Linus Torvalds](/assets/img/avatar_default.png)
Core changes: - Add a new API for explicitly naming GPIO consumers, when needed. - Don't let userspace set values on input lines. While we do not think anyone would do this crazy thing we better plug the hole before someone uses it and think it's a nifty feature. - Avoid calling chip->request() for unused GPIOs. New drivers/subdrivers: - The Mediatek MT7621 is supported which is a big win for OpenWRT and similar router distributions using this chip, as it seems every major router manufacturer on the planet has made products using this chip: https://wikidevi.com/wiki/MediaTek_MT7621 - The Tegra 194 is now supported. - The IT87 driver now supports IT8786E and IT8718F super-IO chips. - Add support for Rockchip RK3328 in the syscon GPIO driver. Driver changes: - Handle the get/set_multiple() properly on MMIO chips with inverted direction registers. We didn't have this problem until a new chip appear that has get/set registers AND inverted direction bits, OK now we handle it. - A patch series making more error codes percolate upward properly for different errors on gpiochip_lock_as_irq(). - Get/set multiple for the OMAP driver, accelerating these multiple line operations if possible. - A coprocessor interface for the Aspeed driver. Sometimes a few GPIO lines need to be grabbed by a co-processor for doing automated tasks, sometimes they are available as GPIO lines. By adding an explicit API in this driver we make it possible for the two line consumers to coexist. (This work was made available on the ib-aspeed branch, which may be appearing in other pull requests.) - Implemented .get_direction() and open drain in the SCH311x driver. - Continuing cleanup of included headers in GPIO drivers. -----BEGIN PGP SIGNATURE----- iQIcBAABAgAGBQJbdDIRAAoJEEEQszewGV1zSVcP/j+dj4HL6R1l8nK4pSqDhY++ Sz7TS5sg7IKa5uLQa7fiheOWllwxJy/gwZ73GjHDxbkT3pol2MlL8ByxC9u7gmm8 4N4xpW0gxO5vMbkbwVj/BdL6qN//JNiwlfp+RtHO74rjUIBgc2At1qL6vul5FEPm T1HUuyzpZ/jd/+CyGR4kg1FrvncMUrStQOdKWN4pI8qFEzFfsGXSeJ+GCBSCjYwD A2Ybad6uuBfdTjrWp2AV4GpKmdKwFeQPzPjm8/CKi97nyeOckNYjDJ+M/1xUR+bb sghn3yJf7+FKO8Qmh+ATvjauPBuDbX5d39FgmFEJRk+ay4Uf2GviroHlwzyWjOi2 5TUaRBubTJM8wFXICCvFvoK8CYLfJEmjJjkHeL12lkkmOlzlCRtcQ0aOLFM+37Ga T7Z6uloEbFK6lT1P6Q/1pfCEUOhofWKdwlWaPxs+7slhKojVJw092wu7J+arKoX9 uLTIe9qAgi3pDRlAkZLrnNwoKTXm18K8KtTv/Uiq8n+s+JRuxA9pAoki5u242lXF ow22OnTgGE3hc2D3o4H1yUPZYoxG9H6iDdir0eEnZpp61xboj44iRgvyDu4LxajS mPOtigcu2qaCEx6EDHTgLIvlKsyQAJmsb0cZ6K4OM3EtUMDfC3WbBzs/VVF//pUa rb+6ruWdwkzXd+ZrnvBq =4+uQ -----END PGP SIGNATURE----- Merge tag 'gpio-v4.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio Pull GPIO updates from Linus Walleij: "This is the bulk of GPIO changes for the v4.19 kernel cycle. I don't know if anything in particular stands out. Maybe the Aspeed coprocessor thing from Benji: Aspeed is doing baseboard management chips (BMC's) for servers etc. These Aspeed's are ARM processors that exist inside (I guess) Intel servers, and they are moving forward to using mainline Linux in those. This is one of the pieces of the puzzle to achive that. They are doing OpenBMC, it's pretty cool: https://lwn.net/Articles/683320/ Summary: Core changes: - Add a new API for explicitly naming GPIO consumers, when needed. - Don't let userspace set values on input lines. While we do not think anyone would do this crazy thing we better plug the hole before someone uses it and think it's a nifty feature. - Avoid calling chip->request() for unused GPIOs. New drivers/subdrivers: - The Mediatek MT7621 is supported which is a big win for OpenWRT and similar router distributions using this chip, as it seems every major router manufacturer on the planet has made products using this chip: https://wikidevi.com/wiki/MediaTek_MT7621 - The Tegra 194 is now supported. - The IT87 driver now supports IT8786E and IT8718F super-IO chips. - Add support for Rockchip RK3328 in the syscon GPIO driver. Driver changes: - Handle the get/set_multiple() properly on MMIO chips with inverted direction registers. We didn't have this problem until a new chip appear that has get/set registers AND inverted direction bits, OK now we handle it. - A patch series making more error codes percolate upward properly for different errors on gpiochip_lock_as_irq(). - Get/set multiple for the OMAP driver, accelerating these multiple line operations if possible. - A coprocessor interface for the Aspeed driver. Sometimes a few GPIO lines need to be grabbed by a co-processor for doing automated tasks, sometimes they are available as GPIO lines. By adding an explicit API in this driver we make it possible for the two line consumers to coexist. (This work was made available on the ib-aspeed branch, which may be appearing in other pull requests.) - Implemented .get_direction() and open drain in the SCH311x driver. - Continuing cleanup of included headers in GPIO drivers" * tag 'gpio-v4.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (80 commits) gpio: it87: Add support for IT8613 gpio: it87: add support for IT8718F Super I/O. gpiolib: Avoid calling chip->request() for unused gpios gpio: tegra: Include the right header gpio: mmio: Fix up inverted direction registers gpio: xilinx: Use the right include gpio: timberdale: Include the right header gpio: tb10x: Use the right include gpiolib: Fix of_node inconsistency gpio: vr41xx: Bail out on gpiochip_lock_as_irq() error gpio: uniphier: Bail out on gpiochip_lock_as_irq() error gpio: xgene-sb: Don't shadow error code of gpiochip_lock_as_irq() gpio: em: Don't shadow error code of gpiochip_lock_as_irq() gpio: dwapb: Don't shadow error code of gpiochip_lock_as_irq() gpio: bcm-kona: Don't shadow error code of gpiochip_lock_as_irq() gpiolib: Don't shadow error code of gpiochip_lock_as_irq() gpio: syscon: rockchip: add GRF GPIO support for rk3328 gpio: omap: Add get/set_multiple() callbacks gpio: pxa: remove set but not used variable 'gpio_offset' gpio-it87: add support for IT8786E Super I/O ...
715 lines
19 KiB
C
715 lines
19 KiB
C
/*
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* arch/arm/mach-tegra/gpio.c
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*
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* Copyright (c) 2010 Google, Inc
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*
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* Author:
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* Erik Gilling <konkers@google.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/gpio/driver.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/module.h>
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#include <linux/irqdomain.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/pm.h>
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#define GPIO_BANK(x) ((x) >> 5)
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#define GPIO_PORT(x) (((x) >> 3) & 0x3)
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#define GPIO_BIT(x) ((x) & 0x7)
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#define GPIO_REG(tgi, x) (GPIO_BANK(x) * tgi->soc->bank_stride + \
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GPIO_PORT(x) * 4)
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#define GPIO_CNF(t, x) (GPIO_REG(t, x) + 0x00)
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#define GPIO_OE(t, x) (GPIO_REG(t, x) + 0x10)
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#define GPIO_OUT(t, x) (GPIO_REG(t, x) + 0X20)
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#define GPIO_IN(t, x) (GPIO_REG(t, x) + 0x30)
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#define GPIO_INT_STA(t, x) (GPIO_REG(t, x) + 0x40)
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#define GPIO_INT_ENB(t, x) (GPIO_REG(t, x) + 0x50)
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#define GPIO_INT_LVL(t, x) (GPIO_REG(t, x) + 0x60)
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#define GPIO_INT_CLR(t, x) (GPIO_REG(t, x) + 0x70)
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#define GPIO_DBC_CNT(t, x) (GPIO_REG(t, x) + 0xF0)
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#define GPIO_MSK_CNF(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x00)
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#define GPIO_MSK_OE(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x10)
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#define GPIO_MSK_OUT(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0X20)
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#define GPIO_MSK_DBC_EN(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x30)
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#define GPIO_MSK_INT_STA(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x40)
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#define GPIO_MSK_INT_ENB(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x50)
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#define GPIO_MSK_INT_LVL(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x60)
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#define GPIO_INT_LVL_MASK 0x010101
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#define GPIO_INT_LVL_EDGE_RISING 0x000101
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#define GPIO_INT_LVL_EDGE_FALLING 0x000100
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#define GPIO_INT_LVL_EDGE_BOTH 0x010100
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#define GPIO_INT_LVL_LEVEL_HIGH 0x000001
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#define GPIO_INT_LVL_LEVEL_LOW 0x000000
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struct tegra_gpio_info;
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struct tegra_gpio_bank {
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unsigned int bank;
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unsigned int irq;
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spinlock_t lvl_lock[4];
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spinlock_t dbc_lock[4]; /* Lock for updating debounce count register */
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#ifdef CONFIG_PM_SLEEP
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u32 cnf[4];
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u32 out[4];
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u32 oe[4];
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u32 int_enb[4];
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u32 int_lvl[4];
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u32 wake_enb[4];
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u32 dbc_enb[4];
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#endif
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u32 dbc_cnt[4];
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struct tegra_gpio_info *tgi;
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};
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struct tegra_gpio_soc_config {
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bool debounce_supported;
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u32 bank_stride;
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u32 upper_offset;
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};
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struct tegra_gpio_info {
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struct device *dev;
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void __iomem *regs;
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struct irq_domain *irq_domain;
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struct tegra_gpio_bank *bank_info;
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const struct tegra_gpio_soc_config *soc;
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struct gpio_chip gc;
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struct irq_chip ic;
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u32 bank_count;
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};
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static inline void tegra_gpio_writel(struct tegra_gpio_info *tgi,
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u32 val, u32 reg)
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{
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__raw_writel(val, tgi->regs + reg);
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}
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static inline u32 tegra_gpio_readl(struct tegra_gpio_info *tgi, u32 reg)
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{
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return __raw_readl(tgi->regs + reg);
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}
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static unsigned int tegra_gpio_compose(unsigned int bank, unsigned int port,
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unsigned int bit)
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{
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return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);
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}
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static void tegra_gpio_mask_write(struct tegra_gpio_info *tgi, u32 reg,
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unsigned int gpio, u32 value)
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{
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u32 val;
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val = 0x100 << GPIO_BIT(gpio);
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if (value)
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val |= 1 << GPIO_BIT(gpio);
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tegra_gpio_writel(tgi, val, reg);
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}
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static void tegra_gpio_enable(struct tegra_gpio_info *tgi, unsigned int gpio)
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{
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tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 1);
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}
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static void tegra_gpio_disable(struct tegra_gpio_info *tgi, unsigned int gpio)
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{
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tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 0);
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}
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static int tegra_gpio_request(struct gpio_chip *chip, unsigned int offset)
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{
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return pinctrl_gpio_request(offset);
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}
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static void tegra_gpio_free(struct gpio_chip *chip, unsigned int offset)
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{
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struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
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pinctrl_gpio_free(offset);
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tegra_gpio_disable(tgi, offset);
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}
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static void tegra_gpio_set(struct gpio_chip *chip, unsigned int offset,
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int value)
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{
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struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
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tegra_gpio_mask_write(tgi, GPIO_MSK_OUT(tgi, offset), offset, value);
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}
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static int tegra_gpio_get(struct gpio_chip *chip, unsigned int offset)
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{
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struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
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unsigned int bval = BIT(GPIO_BIT(offset));
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/* If gpio is in output mode then read from the out value */
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if (tegra_gpio_readl(tgi, GPIO_OE(tgi, offset)) & bval)
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return !!(tegra_gpio_readl(tgi, GPIO_OUT(tgi, offset)) & bval);
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return !!(tegra_gpio_readl(tgi, GPIO_IN(tgi, offset)) & bval);
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}
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static int tegra_gpio_direction_input(struct gpio_chip *chip,
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unsigned int offset)
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{
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struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
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tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 0);
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tegra_gpio_enable(tgi, offset);
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return 0;
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}
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static int tegra_gpio_direction_output(struct gpio_chip *chip,
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unsigned int offset,
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int value)
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{
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struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
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tegra_gpio_set(chip, offset, value);
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tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 1);
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tegra_gpio_enable(tgi, offset);
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return 0;
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}
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static int tegra_gpio_get_direction(struct gpio_chip *chip,
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unsigned int offset)
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{
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struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
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u32 pin_mask = BIT(GPIO_BIT(offset));
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u32 cnf, oe;
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cnf = tegra_gpio_readl(tgi, GPIO_CNF(tgi, offset));
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if (!(cnf & pin_mask))
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return -EINVAL;
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oe = tegra_gpio_readl(tgi, GPIO_OE(tgi, offset));
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return !(oe & pin_mask);
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}
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static int tegra_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset,
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unsigned int debounce)
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{
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struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
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struct tegra_gpio_bank *bank = &tgi->bank_info[GPIO_BANK(offset)];
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unsigned int debounce_ms = DIV_ROUND_UP(debounce, 1000);
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unsigned long flags;
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unsigned int port;
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if (!debounce_ms) {
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tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset),
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offset, 0);
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return 0;
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}
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debounce_ms = min(debounce_ms, 255U);
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port = GPIO_PORT(offset);
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/* There is only one debounce count register per port and hence
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* set the maximum of current and requested debounce time.
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*/
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spin_lock_irqsave(&bank->dbc_lock[port], flags);
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if (bank->dbc_cnt[port] < debounce_ms) {
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tegra_gpio_writel(tgi, debounce_ms, GPIO_DBC_CNT(tgi, offset));
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bank->dbc_cnt[port] = debounce_ms;
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}
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spin_unlock_irqrestore(&bank->dbc_lock[port], flags);
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tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset), offset, 1);
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return 0;
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}
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static int tegra_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
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unsigned long config)
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{
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u32 debounce;
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if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
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return -ENOTSUPP;
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debounce = pinconf_to_config_argument(config);
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return tegra_gpio_set_debounce(chip, offset, debounce);
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}
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static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
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{
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struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
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return irq_find_mapping(tgi->irq_domain, offset);
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}
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static void tegra_gpio_irq_ack(struct irq_data *d)
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{
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struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
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struct tegra_gpio_info *tgi = bank->tgi;
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unsigned int gpio = d->hwirq;
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tegra_gpio_writel(tgi, 1 << GPIO_BIT(gpio), GPIO_INT_CLR(tgi, gpio));
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}
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static void tegra_gpio_irq_mask(struct irq_data *d)
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{
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struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
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struct tegra_gpio_info *tgi = bank->tgi;
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unsigned int gpio = d->hwirq;
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tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 0);
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}
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static void tegra_gpio_irq_unmask(struct irq_data *d)
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{
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struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
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struct tegra_gpio_info *tgi = bank->tgi;
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unsigned int gpio = d->hwirq;
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tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 1);
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}
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static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
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{
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unsigned int gpio = d->hwirq, port = GPIO_PORT(gpio), lvl_type;
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struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
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struct tegra_gpio_info *tgi = bank->tgi;
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unsigned long flags;
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u32 val;
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int ret;
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switch (type & IRQ_TYPE_SENSE_MASK) {
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case IRQ_TYPE_EDGE_RISING:
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lvl_type = GPIO_INT_LVL_EDGE_RISING;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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lvl_type = GPIO_INT_LVL_EDGE_FALLING;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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lvl_type = GPIO_INT_LVL_EDGE_BOTH;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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lvl_type = GPIO_INT_LVL_LEVEL_HIGH;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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lvl_type = GPIO_INT_LVL_LEVEL_LOW;
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break;
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default:
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return -EINVAL;
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}
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spin_lock_irqsave(&bank->lvl_lock[port], flags);
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val = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio));
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val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
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val |= lvl_type << GPIO_BIT(gpio);
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tegra_gpio_writel(tgi, val, GPIO_INT_LVL(tgi, gpio));
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spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
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tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, gpio), gpio, 0);
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tegra_gpio_enable(tgi, gpio);
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ret = gpiochip_lock_as_irq(&tgi->gc, gpio);
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if (ret) {
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dev_err(tgi->dev,
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"unable to lock Tegra GPIO %u as IRQ\n", gpio);
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tegra_gpio_disable(tgi, gpio);
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return ret;
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}
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if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
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irq_set_handler_locked(d, handle_level_irq);
|
|
else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
|
|
irq_set_handler_locked(d, handle_edge_irq);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void tegra_gpio_irq_shutdown(struct irq_data *d)
|
|
{
|
|
struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
|
|
struct tegra_gpio_info *tgi = bank->tgi;
|
|
unsigned int gpio = d->hwirq;
|
|
|
|
gpiochip_unlock_as_irq(&tgi->gc, gpio);
|
|
}
|
|
|
|
static void tegra_gpio_irq_handler(struct irq_desc *desc)
|
|
{
|
|
unsigned int port, pin, gpio;
|
|
bool unmasked = false;
|
|
u32 lvl;
|
|
unsigned long sta;
|
|
struct irq_chip *chip = irq_desc_get_chip(desc);
|
|
struct tegra_gpio_bank *bank = irq_desc_get_handler_data(desc);
|
|
struct tegra_gpio_info *tgi = bank->tgi;
|
|
|
|
chained_irq_enter(chip, desc);
|
|
|
|
for (port = 0; port < 4; port++) {
|
|
gpio = tegra_gpio_compose(bank->bank, port, 0);
|
|
sta = tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)) &
|
|
tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio));
|
|
lvl = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio));
|
|
|
|
for_each_set_bit(pin, &sta, 8) {
|
|
tegra_gpio_writel(tgi, 1 << pin,
|
|
GPIO_INT_CLR(tgi, gpio));
|
|
|
|
/* if gpio is edge triggered, clear condition
|
|
* before executing the handler so that we don't
|
|
* miss edges
|
|
*/
|
|
if (!unmasked && lvl & (0x100 << pin)) {
|
|
unmasked = true;
|
|
chained_irq_exit(chip, desc);
|
|
}
|
|
|
|
generic_handle_irq(irq_find_mapping(tgi->irq_domain,
|
|
gpio + pin));
|
|
}
|
|
}
|
|
|
|
if (!unmasked)
|
|
chained_irq_exit(chip, desc);
|
|
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int tegra_gpio_resume(struct device *dev)
|
|
{
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
struct tegra_gpio_info *tgi = platform_get_drvdata(pdev);
|
|
unsigned long flags;
|
|
unsigned int b, p;
|
|
|
|
local_irq_save(flags);
|
|
|
|
for (b = 0; b < tgi->bank_count; b++) {
|
|
struct tegra_gpio_bank *bank = &tgi->bank_info[b];
|
|
|
|
for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
|
|
unsigned int gpio = (b << 5) | (p << 3);
|
|
|
|
tegra_gpio_writel(tgi, bank->cnf[p],
|
|
GPIO_CNF(tgi, gpio));
|
|
|
|
if (tgi->soc->debounce_supported) {
|
|
tegra_gpio_writel(tgi, bank->dbc_cnt[p],
|
|
GPIO_DBC_CNT(tgi, gpio));
|
|
tegra_gpio_writel(tgi, bank->dbc_enb[p],
|
|
GPIO_MSK_DBC_EN(tgi, gpio));
|
|
}
|
|
|
|
tegra_gpio_writel(tgi, bank->out[p],
|
|
GPIO_OUT(tgi, gpio));
|
|
tegra_gpio_writel(tgi, bank->oe[p],
|
|
GPIO_OE(tgi, gpio));
|
|
tegra_gpio_writel(tgi, bank->int_lvl[p],
|
|
GPIO_INT_LVL(tgi, gpio));
|
|
tegra_gpio_writel(tgi, bank->int_enb[p],
|
|
GPIO_INT_ENB(tgi, gpio));
|
|
}
|
|
}
|
|
|
|
local_irq_restore(flags);
|
|
return 0;
|
|
}
|
|
|
|
static int tegra_gpio_suspend(struct device *dev)
|
|
{
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
struct tegra_gpio_info *tgi = platform_get_drvdata(pdev);
|
|
unsigned long flags;
|
|
unsigned int b, p;
|
|
|
|
local_irq_save(flags);
|
|
for (b = 0; b < tgi->bank_count; b++) {
|
|
struct tegra_gpio_bank *bank = &tgi->bank_info[b];
|
|
|
|
for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
|
|
unsigned int gpio = (b << 5) | (p << 3);
|
|
|
|
bank->cnf[p] = tegra_gpio_readl(tgi,
|
|
GPIO_CNF(tgi, gpio));
|
|
bank->out[p] = tegra_gpio_readl(tgi,
|
|
GPIO_OUT(tgi, gpio));
|
|
bank->oe[p] = tegra_gpio_readl(tgi,
|
|
GPIO_OE(tgi, gpio));
|
|
if (tgi->soc->debounce_supported) {
|
|
bank->dbc_enb[p] = tegra_gpio_readl(tgi,
|
|
GPIO_MSK_DBC_EN(tgi, gpio));
|
|
bank->dbc_enb[p] = (bank->dbc_enb[p] << 8) |
|
|
bank->dbc_enb[p];
|
|
}
|
|
|
|
bank->int_enb[p] = tegra_gpio_readl(tgi,
|
|
GPIO_INT_ENB(tgi, gpio));
|
|
bank->int_lvl[p] = tegra_gpio_readl(tgi,
|
|
GPIO_INT_LVL(tgi, gpio));
|
|
|
|
/* Enable gpio irq for wake up source */
|
|
tegra_gpio_writel(tgi, bank->wake_enb[p],
|
|
GPIO_INT_ENB(tgi, gpio));
|
|
}
|
|
}
|
|
local_irq_restore(flags);
|
|
return 0;
|
|
}
|
|
|
|
static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
|
|
{
|
|
struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
|
|
unsigned int gpio = d->hwirq;
|
|
u32 port, bit, mask;
|
|
|
|
port = GPIO_PORT(gpio);
|
|
bit = GPIO_BIT(gpio);
|
|
mask = BIT(bit);
|
|
|
|
if (enable)
|
|
bank->wake_enb[port] |= mask;
|
|
else
|
|
bank->wake_enb[port] &= ~mask;
|
|
|
|
return irq_set_irq_wake(bank->irq, enable);
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_DEBUG_FS
|
|
|
|
#include <linux/debugfs.h>
|
|
#include <linux/seq_file.h>
|
|
|
|
static int tegra_dbg_gpio_show(struct seq_file *s, void *unused)
|
|
{
|
|
struct tegra_gpio_info *tgi = s->private;
|
|
unsigned int i, j;
|
|
|
|
for (i = 0; i < tgi->bank_count; i++) {
|
|
for (j = 0; j < 4; j++) {
|
|
unsigned int gpio = tegra_gpio_compose(i, j, 0);
|
|
|
|
seq_printf(s,
|
|
"%u:%u %02x %02x %02x %02x %02x %02x %06x\n",
|
|
i, j,
|
|
tegra_gpio_readl(tgi, GPIO_CNF(tgi, gpio)),
|
|
tegra_gpio_readl(tgi, GPIO_OE(tgi, gpio)),
|
|
tegra_gpio_readl(tgi, GPIO_OUT(tgi, gpio)),
|
|
tegra_gpio_readl(tgi, GPIO_IN(tgi, gpio)),
|
|
tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)),
|
|
tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio)),
|
|
tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio)));
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
DEFINE_SHOW_ATTRIBUTE(tegra_dbg_gpio);
|
|
|
|
static void tegra_gpio_debuginit(struct tegra_gpio_info *tgi)
|
|
{
|
|
(void) debugfs_create_file("tegra_gpio", 0444,
|
|
NULL, tgi, &tegra_dbg_gpio_fops);
|
|
}
|
|
|
|
#else
|
|
|
|
static inline void tegra_gpio_debuginit(struct tegra_gpio_info *tgi)
|
|
{
|
|
}
|
|
|
|
#endif
|
|
|
|
static const struct dev_pm_ops tegra_gpio_pm_ops = {
|
|
SET_SYSTEM_SLEEP_PM_OPS(tegra_gpio_suspend, tegra_gpio_resume)
|
|
};
|
|
|
|
static int tegra_gpio_probe(struct platform_device *pdev)
|
|
{
|
|
struct tegra_gpio_info *tgi;
|
|
struct resource *res;
|
|
struct tegra_gpio_bank *bank;
|
|
unsigned int gpio, i, j;
|
|
int ret;
|
|
|
|
tgi = devm_kzalloc(&pdev->dev, sizeof(*tgi), GFP_KERNEL);
|
|
if (!tgi)
|
|
return -ENODEV;
|
|
|
|
tgi->soc = of_device_get_match_data(&pdev->dev);
|
|
tgi->dev = &pdev->dev;
|
|
|
|
ret = platform_irq_count(pdev);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
tgi->bank_count = ret;
|
|
|
|
if (!tgi->bank_count) {
|
|
dev_err(&pdev->dev, "Missing IRQ resource\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
tgi->gc.label = "tegra-gpio";
|
|
tgi->gc.request = tegra_gpio_request;
|
|
tgi->gc.free = tegra_gpio_free;
|
|
tgi->gc.direction_input = tegra_gpio_direction_input;
|
|
tgi->gc.get = tegra_gpio_get;
|
|
tgi->gc.direction_output = tegra_gpio_direction_output;
|
|
tgi->gc.set = tegra_gpio_set;
|
|
tgi->gc.get_direction = tegra_gpio_get_direction;
|
|
tgi->gc.to_irq = tegra_gpio_to_irq;
|
|
tgi->gc.base = 0;
|
|
tgi->gc.ngpio = tgi->bank_count * 32;
|
|
tgi->gc.parent = &pdev->dev;
|
|
tgi->gc.of_node = pdev->dev.of_node;
|
|
|
|
tgi->ic.name = "GPIO";
|
|
tgi->ic.irq_ack = tegra_gpio_irq_ack;
|
|
tgi->ic.irq_mask = tegra_gpio_irq_mask;
|
|
tgi->ic.irq_unmask = tegra_gpio_irq_unmask;
|
|
tgi->ic.irq_set_type = tegra_gpio_irq_set_type;
|
|
tgi->ic.irq_shutdown = tegra_gpio_irq_shutdown;
|
|
#ifdef CONFIG_PM_SLEEP
|
|
tgi->ic.irq_set_wake = tegra_gpio_irq_set_wake;
|
|
#endif
|
|
|
|
platform_set_drvdata(pdev, tgi);
|
|
|
|
if (tgi->soc->debounce_supported)
|
|
tgi->gc.set_config = tegra_gpio_set_config;
|
|
|
|
tgi->bank_info = devm_kcalloc(&pdev->dev, tgi->bank_count,
|
|
sizeof(*tgi->bank_info), GFP_KERNEL);
|
|
if (!tgi->bank_info)
|
|
return -ENOMEM;
|
|
|
|
tgi->irq_domain = irq_domain_add_linear(pdev->dev.of_node,
|
|
tgi->gc.ngpio,
|
|
&irq_domain_simple_ops, NULL);
|
|
if (!tgi->irq_domain)
|
|
return -ENODEV;
|
|
|
|
for (i = 0; i < tgi->bank_count; i++) {
|
|
ret = platform_get_irq(pdev, i);
|
|
if (ret < 0) {
|
|
dev_err(&pdev->dev, "Missing IRQ resource: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
bank = &tgi->bank_info[i];
|
|
bank->bank = i;
|
|
bank->irq = ret;
|
|
bank->tgi = tgi;
|
|
}
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
tgi->regs = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(tgi->regs))
|
|
return PTR_ERR(tgi->regs);
|
|
|
|
for (i = 0; i < tgi->bank_count; i++) {
|
|
for (j = 0; j < 4; j++) {
|
|
int gpio = tegra_gpio_compose(i, j, 0);
|
|
|
|
tegra_gpio_writel(tgi, 0x00, GPIO_INT_ENB(tgi, gpio));
|
|
}
|
|
}
|
|
|
|
ret = devm_gpiochip_add_data(&pdev->dev, &tgi->gc, tgi);
|
|
if (ret < 0) {
|
|
irq_domain_remove(tgi->irq_domain);
|
|
return ret;
|
|
}
|
|
|
|
for (gpio = 0; gpio < tgi->gc.ngpio; gpio++) {
|
|
int irq = irq_create_mapping(tgi->irq_domain, gpio);
|
|
/* No validity check; all Tegra GPIOs are valid IRQs */
|
|
|
|
bank = &tgi->bank_info[GPIO_BANK(gpio)];
|
|
|
|
irq_set_chip_data(irq, bank);
|
|
irq_set_chip_and_handler(irq, &tgi->ic, handle_simple_irq);
|
|
}
|
|
|
|
for (i = 0; i < tgi->bank_count; i++) {
|
|
bank = &tgi->bank_info[i];
|
|
|
|
irq_set_chained_handler_and_data(bank->irq,
|
|
tegra_gpio_irq_handler, bank);
|
|
|
|
for (j = 0; j < 4; j++) {
|
|
spin_lock_init(&bank->lvl_lock[j]);
|
|
spin_lock_init(&bank->dbc_lock[j]);
|
|
}
|
|
}
|
|
|
|
tegra_gpio_debuginit(tgi);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct tegra_gpio_soc_config tegra20_gpio_config = {
|
|
.bank_stride = 0x80,
|
|
.upper_offset = 0x800,
|
|
};
|
|
|
|
static const struct tegra_gpio_soc_config tegra30_gpio_config = {
|
|
.bank_stride = 0x100,
|
|
.upper_offset = 0x80,
|
|
};
|
|
|
|
static const struct tegra_gpio_soc_config tegra210_gpio_config = {
|
|
.debounce_supported = true,
|
|
.bank_stride = 0x100,
|
|
.upper_offset = 0x80,
|
|
};
|
|
|
|
static const struct of_device_id tegra_gpio_of_match[] = {
|
|
{ .compatible = "nvidia,tegra210-gpio", .data = &tegra210_gpio_config },
|
|
{ .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config },
|
|
{ .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config },
|
|
{ },
|
|
};
|
|
|
|
static struct platform_driver tegra_gpio_driver = {
|
|
.driver = {
|
|
.name = "tegra-gpio",
|
|
.pm = &tegra_gpio_pm_ops,
|
|
.of_match_table = tegra_gpio_of_match,
|
|
},
|
|
.probe = tegra_gpio_probe,
|
|
};
|
|
|
|
static int __init tegra_gpio_init(void)
|
|
{
|
|
return platform_driver_register(&tegra_gpio_driver);
|
|
}
|
|
subsys_initcall(tegra_gpio_init);
|