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![Marc Zyngier](/assets/img/avatar_default.png)
Allocating a minimum of 32 LPIs per PCI device, let's reduce it to be just 1, as most devices do not need that many interrupts. We still have to special-case DevID 0, as there is plenty of broken HW around where the PCI RID is not presented as a DevID to the ITS, and all the devices are presented as DevID 0. In this case, we keep the 32 minimal allocation. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
208 lines
5.3 KiB
C
208 lines
5.3 KiB
C
/*
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* Copyright (C) 2013-2015 ARM Limited, All Rights Reserved.
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/acpi_iort.h>
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#include <linux/msi.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/of_pci.h>
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static void its_mask_msi_irq(struct irq_data *d)
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{
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pci_msi_mask_irq(d);
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irq_chip_mask_parent(d);
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}
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static void its_unmask_msi_irq(struct irq_data *d)
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{
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pci_msi_unmask_irq(d);
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irq_chip_unmask_parent(d);
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}
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static struct irq_chip its_msi_irq_chip = {
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.name = "ITS-MSI",
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.irq_unmask = its_unmask_msi_irq,
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.irq_mask = its_mask_msi_irq,
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.irq_eoi = irq_chip_eoi_parent,
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.irq_write_msi_msg = pci_msi_domain_write_msg,
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};
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static int its_pci_msi_vec_count(struct pci_dev *pdev, void *data)
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{
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int msi, msix, *count = data;
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msi = max(pci_msi_vec_count(pdev), 0);
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msix = max(pci_msix_vec_count(pdev), 0);
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*count += max(msi, msix);
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return 0;
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}
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static int its_get_pci_alias(struct pci_dev *pdev, u16 alias, void *data)
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{
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struct pci_dev **alias_dev = data;
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*alias_dev = pdev;
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return 0;
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}
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static int its_pci_msi_prepare(struct irq_domain *domain, struct device *dev,
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int nvec, msi_alloc_info_t *info)
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{
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struct pci_dev *pdev, *alias_dev;
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struct msi_domain_info *msi_info;
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int alias_count = 0, minnvec = 1;
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if (!dev_is_pci(dev))
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return -EINVAL;
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msi_info = msi_get_domain_info(domain->parent);
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pdev = to_pci_dev(dev);
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/*
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* If pdev is downstream of any aliasing bridges, take an upper
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* bound of how many other vectors could map to the same DevID.
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*/
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pci_for_each_dma_alias(pdev, its_get_pci_alias, &alias_dev);
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if (alias_dev != pdev && alias_dev->subordinate)
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pci_walk_bus(alias_dev->subordinate, its_pci_msi_vec_count,
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&alias_count);
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/* ITS specific DeviceID, as the core ITS ignores dev. */
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info->scratchpad[0].ul = pci_msi_domain_get_msi_rid(domain, pdev);
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/*
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* Always allocate a power of 2, and special case device 0 for
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* broken systems where the DevID is not wired (and all devices
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* appear as DevID 0). For that reason, we generously allocate a
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* minimum of 32 MSIs for DevID 0. If you want more because all
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* your devices are aliasing to DevID 0, consider fixing your HW.
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*/
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nvec = max(nvec, alias_count);
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if (!info->scratchpad[0].ul)
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minnvec = 32;
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nvec = max_t(int, minnvec, roundup_pow_of_two(nvec));
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return msi_info->ops->msi_prepare(domain->parent, dev, nvec, info);
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}
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static struct msi_domain_ops its_pci_msi_ops = {
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.msi_prepare = its_pci_msi_prepare,
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};
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static struct msi_domain_info its_pci_msi_domain_info = {
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.flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
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MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX),
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.ops = &its_pci_msi_ops,
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.chip = &its_msi_irq_chip,
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};
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static struct of_device_id its_device_id[] = {
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{ .compatible = "arm,gic-v3-its", },
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{},
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};
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static int __init its_pci_msi_init_one(struct fwnode_handle *handle,
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const char *name)
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{
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struct irq_domain *parent;
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parent = irq_find_matching_fwnode(handle, DOMAIN_BUS_NEXUS);
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if (!parent || !msi_get_domain_info(parent)) {
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pr_err("%s: Unable to locate ITS domain\n", name);
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return -ENXIO;
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}
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if (!pci_msi_create_irq_domain(handle, &its_pci_msi_domain_info,
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parent)) {
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pr_err("%s: Unable to create PCI domain\n", name);
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return -ENOMEM;
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}
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return 0;
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}
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static int __init its_pci_of_msi_init(void)
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{
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struct device_node *np;
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for (np = of_find_matching_node(NULL, its_device_id); np;
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np = of_find_matching_node(np, its_device_id)) {
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if (!of_device_is_available(np))
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continue;
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if (!of_property_read_bool(np, "msi-controller"))
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continue;
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if (its_pci_msi_init_one(of_node_to_fwnode(np), np->full_name))
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continue;
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pr_info("PCI/MSI: %pOF domain created\n", np);
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}
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return 0;
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}
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#ifdef CONFIG_ACPI
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static int __init
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its_pci_msi_parse_madt(struct acpi_subtable_header *header,
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const unsigned long end)
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{
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struct acpi_madt_generic_translator *its_entry;
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struct fwnode_handle *dom_handle;
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const char *node_name;
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int err = -ENXIO;
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its_entry = (struct acpi_madt_generic_translator *)header;
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node_name = kasprintf(GFP_KERNEL, "ITS@0x%lx",
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(long)its_entry->base_address);
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dom_handle = iort_find_domain_token(its_entry->translation_id);
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if (!dom_handle) {
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pr_err("%s: Unable to locate ITS domain handle\n", node_name);
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goto out;
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}
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err = its_pci_msi_init_one(dom_handle, node_name);
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if (!err)
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pr_info("PCI/MSI: %s domain created\n", node_name);
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out:
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kfree(node_name);
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return err;
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}
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static int __init its_pci_acpi_msi_init(void)
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{
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acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_TRANSLATOR,
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its_pci_msi_parse_madt, 0);
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return 0;
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}
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#else
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static int __init its_pci_acpi_msi_init(void)
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{
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return 0;
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}
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#endif
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static int __init its_pci_msi_init(void)
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{
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its_pci_of_msi_init();
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its_pci_acpi_msi_init();
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return 0;
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}
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early_initcall(its_pci_msi_init);
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