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![Matt Redfearn](/assets/img/avatar_default.png)
Commit7778c4b27c
("irqchip: mips-gic: Use pcpu_masks to avoid reading GIC_SH_MASK*") removed the read of the hardware mask register when handling shared interrupts, instead using the driver's shadow pcpu_masks entry as the effective mask. Unfortunately this did not take account of the write to pcpu_masks during gic_shared_irq_domain_map, which effectively unmasks the interrupt early. If an interrupt is asserted, gic_handle_shared_int decodes and processes the interrupt even though it has not yet been unmasked via gic_unmask_irq, which also sets the appropriate bit in pcpu_masks. On the MIPS Boston board, when a console command line of "console=ttyS0,115200n8r" is passed, the modem status IRQ is enabled in the UART, which is immediately raised to the GIC. The interrupt has been mapped, but no handler has yet been registered, nor is it expected to be unmasked. However, the write to pcpu_masks in gic_shared_irq_domain_map has effectively unmasked it, resulting in endless reports of: [ 5.058454] irq 13, desc: ffffffff80a7ad80, depth: 1, count: 0, unhandled: 0 [ 5.062057] ->handle_irq(): ffffffff801b1838, [ 5.062175] handle_bad_irq+0x0/0x2c0 Where IRQ 13 is the UART interrupt. To fix this, just remove the write to pcpu_masks in gic_shared_irq_domain_map. The existing write in gic_unmask_irq is the correct place for what is now the effective unmasking. Cc: stable@vger.kernel.org Fixes:7778c4b27c
("irqchip: mips-gic: Use pcpu_masks to avoid reading GIC_SH_MASK*") Signed-off-by: Matt Redfearn <matt.redfearn@mips.com> Reviewed-by: Paul Burton <paul.burton@mips.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
805 lines
20 KiB
C
805 lines
20 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org)
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* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
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*/
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#define pr_fmt(fmt) "irq-mips-gic: " fmt
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#include <linux/bitmap.h>
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#include <linux/clocksource.h>
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#include <linux/cpuhotplug.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/of_address.h>
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#include <linux/percpu.h>
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#include <linux/sched.h>
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#include <linux/smp.h>
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#include <asm/mips-cps.h>
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#include <asm/setup.h>
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#include <asm/traps.h>
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#include <dt-bindings/interrupt-controller/mips-gic.h>
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#define GIC_MAX_INTRS 256
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#define GIC_MAX_LONGS BITS_TO_LONGS(GIC_MAX_INTRS)
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/* Add 2 to convert GIC CPU pin to core interrupt */
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#define GIC_CPU_PIN_OFFSET 2
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/* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */
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#define GIC_PIN_TO_VEC_OFFSET 1
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/* Convert between local/shared IRQ number and GIC HW IRQ number. */
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#define GIC_LOCAL_HWIRQ_BASE 0
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#define GIC_LOCAL_TO_HWIRQ(x) (GIC_LOCAL_HWIRQ_BASE + (x))
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#define GIC_HWIRQ_TO_LOCAL(x) ((x) - GIC_LOCAL_HWIRQ_BASE)
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#define GIC_SHARED_HWIRQ_BASE GIC_NUM_LOCAL_INTRS
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#define GIC_SHARED_TO_HWIRQ(x) (GIC_SHARED_HWIRQ_BASE + (x))
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#define GIC_HWIRQ_TO_SHARED(x) ((x) - GIC_SHARED_HWIRQ_BASE)
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void __iomem *mips_gic_base;
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DEFINE_PER_CPU_READ_MOSTLY(unsigned long[GIC_MAX_LONGS], pcpu_masks);
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static DEFINE_SPINLOCK(gic_lock);
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static struct irq_domain *gic_irq_domain;
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static struct irq_domain *gic_ipi_domain;
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static int gic_shared_intrs;
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static unsigned int gic_cpu_pin;
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static unsigned int timer_cpu_pin;
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static struct irq_chip gic_level_irq_controller, gic_edge_irq_controller;
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static DECLARE_BITMAP(ipi_resrv, GIC_MAX_INTRS);
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static DECLARE_BITMAP(ipi_available, GIC_MAX_INTRS);
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static struct gic_all_vpes_chip_data {
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u32 map;
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bool mask;
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} gic_all_vpes_chip_data[GIC_NUM_LOCAL_INTRS];
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static void gic_clear_pcpu_masks(unsigned int intr)
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{
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unsigned int i;
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/* Clear the interrupt's bit in all pcpu_masks */
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for_each_possible_cpu(i)
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clear_bit(intr, per_cpu_ptr(pcpu_masks, i));
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}
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static bool gic_local_irq_is_routable(int intr)
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{
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u32 vpe_ctl;
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/* All local interrupts are routable in EIC mode. */
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if (cpu_has_veic)
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return true;
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vpe_ctl = read_gic_vl_ctl();
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switch (intr) {
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case GIC_LOCAL_INT_TIMER:
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return vpe_ctl & GIC_VX_CTL_TIMER_ROUTABLE;
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case GIC_LOCAL_INT_PERFCTR:
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return vpe_ctl & GIC_VX_CTL_PERFCNT_ROUTABLE;
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case GIC_LOCAL_INT_FDC:
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return vpe_ctl & GIC_VX_CTL_FDC_ROUTABLE;
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case GIC_LOCAL_INT_SWINT0:
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case GIC_LOCAL_INT_SWINT1:
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return vpe_ctl & GIC_VX_CTL_SWINT_ROUTABLE;
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default:
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return true;
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}
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}
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static void gic_bind_eic_interrupt(int irq, int set)
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{
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/* Convert irq vector # to hw int # */
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irq -= GIC_PIN_TO_VEC_OFFSET;
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/* Set irq to use shadow set */
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write_gic_vl_eic_shadow_set(irq, set);
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}
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static void gic_send_ipi(struct irq_data *d, unsigned int cpu)
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{
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irq_hw_number_t hwirq = GIC_HWIRQ_TO_SHARED(irqd_to_hwirq(d));
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write_gic_wedge(GIC_WEDGE_RW | hwirq);
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}
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int gic_get_c0_compare_int(void)
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{
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if (!gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER))
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return MIPS_CPU_IRQ_BASE + cp0_compare_irq;
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return irq_create_mapping(gic_irq_domain,
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GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_TIMER));
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}
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int gic_get_c0_perfcount_int(void)
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{
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if (!gic_local_irq_is_routable(GIC_LOCAL_INT_PERFCTR)) {
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/* Is the performance counter shared with the timer? */
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if (cp0_perfcount_irq < 0)
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return -1;
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return MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
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}
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return irq_create_mapping(gic_irq_domain,
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GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_PERFCTR));
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}
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int gic_get_c0_fdc_int(void)
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{
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if (!gic_local_irq_is_routable(GIC_LOCAL_INT_FDC)) {
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/* Is the FDC IRQ even present? */
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if (cp0_fdc_irq < 0)
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return -1;
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return MIPS_CPU_IRQ_BASE + cp0_fdc_irq;
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}
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return irq_create_mapping(gic_irq_domain,
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GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_FDC));
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}
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static void gic_handle_shared_int(bool chained)
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{
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unsigned int intr, virq;
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unsigned long *pcpu_mask;
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DECLARE_BITMAP(pending, GIC_MAX_INTRS);
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/* Get per-cpu bitmaps */
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pcpu_mask = this_cpu_ptr(pcpu_masks);
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if (mips_cm_is64)
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__ioread64_copy(pending, addr_gic_pend(),
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DIV_ROUND_UP(gic_shared_intrs, 64));
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else
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__ioread32_copy(pending, addr_gic_pend(),
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DIV_ROUND_UP(gic_shared_intrs, 32));
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bitmap_and(pending, pending, pcpu_mask, gic_shared_intrs);
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for_each_set_bit(intr, pending, gic_shared_intrs) {
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virq = irq_linear_revmap(gic_irq_domain,
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GIC_SHARED_TO_HWIRQ(intr));
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if (chained)
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generic_handle_irq(virq);
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else
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do_IRQ(virq);
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}
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}
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static void gic_mask_irq(struct irq_data *d)
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{
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unsigned int intr = GIC_HWIRQ_TO_SHARED(d->hwirq);
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write_gic_rmask(intr);
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gic_clear_pcpu_masks(intr);
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}
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static void gic_unmask_irq(struct irq_data *d)
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{
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unsigned int intr = GIC_HWIRQ_TO_SHARED(d->hwirq);
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unsigned int cpu;
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write_gic_smask(intr);
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gic_clear_pcpu_masks(intr);
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cpu = cpumask_first(irq_data_get_effective_affinity_mask(d));
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set_bit(intr, per_cpu_ptr(pcpu_masks, cpu));
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}
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static void gic_ack_irq(struct irq_data *d)
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{
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unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq);
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write_gic_wedge(irq);
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}
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static int gic_set_type(struct irq_data *d, unsigned int type)
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{
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unsigned int irq, pol, trig, dual;
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unsigned long flags;
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irq = GIC_HWIRQ_TO_SHARED(d->hwirq);
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spin_lock_irqsave(&gic_lock, flags);
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switch (type & IRQ_TYPE_SENSE_MASK) {
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case IRQ_TYPE_EDGE_FALLING:
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pol = GIC_POL_FALLING_EDGE;
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trig = GIC_TRIG_EDGE;
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dual = GIC_DUAL_SINGLE;
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break;
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case IRQ_TYPE_EDGE_RISING:
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pol = GIC_POL_RISING_EDGE;
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trig = GIC_TRIG_EDGE;
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dual = GIC_DUAL_SINGLE;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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pol = 0; /* Doesn't matter */
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trig = GIC_TRIG_EDGE;
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dual = GIC_DUAL_DUAL;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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pol = GIC_POL_ACTIVE_LOW;
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trig = GIC_TRIG_LEVEL;
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dual = GIC_DUAL_SINGLE;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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default:
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pol = GIC_POL_ACTIVE_HIGH;
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trig = GIC_TRIG_LEVEL;
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dual = GIC_DUAL_SINGLE;
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break;
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}
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change_gic_pol(irq, pol);
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change_gic_trig(irq, trig);
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change_gic_dual(irq, dual);
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if (trig == GIC_TRIG_EDGE)
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irq_set_chip_handler_name_locked(d, &gic_edge_irq_controller,
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handle_edge_irq, NULL);
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else
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irq_set_chip_handler_name_locked(d, &gic_level_irq_controller,
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handle_level_irq, NULL);
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spin_unlock_irqrestore(&gic_lock, flags);
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return 0;
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}
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#ifdef CONFIG_SMP
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static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
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bool force)
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{
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unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq);
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unsigned long flags;
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unsigned int cpu;
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cpu = cpumask_first_and(cpumask, cpu_online_mask);
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if (cpu >= NR_CPUS)
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return -EINVAL;
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/* Assumption : cpumask refers to a single CPU */
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spin_lock_irqsave(&gic_lock, flags);
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/* Re-route this IRQ */
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write_gic_map_vp(irq, BIT(mips_cm_vp_id(cpu)));
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/* Update the pcpu_masks */
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gic_clear_pcpu_masks(irq);
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if (read_gic_mask(irq))
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set_bit(irq, per_cpu_ptr(pcpu_masks, cpu));
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irq_data_update_effective_affinity(d, cpumask_of(cpu));
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spin_unlock_irqrestore(&gic_lock, flags);
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return IRQ_SET_MASK_OK;
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}
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#endif
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static struct irq_chip gic_level_irq_controller = {
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.name = "MIPS GIC",
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.irq_mask = gic_mask_irq,
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.irq_unmask = gic_unmask_irq,
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.irq_set_type = gic_set_type,
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#ifdef CONFIG_SMP
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.irq_set_affinity = gic_set_affinity,
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#endif
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};
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static struct irq_chip gic_edge_irq_controller = {
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.name = "MIPS GIC",
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.irq_ack = gic_ack_irq,
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.irq_mask = gic_mask_irq,
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.irq_unmask = gic_unmask_irq,
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.irq_set_type = gic_set_type,
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#ifdef CONFIG_SMP
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.irq_set_affinity = gic_set_affinity,
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#endif
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.ipi_send_single = gic_send_ipi,
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};
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static void gic_handle_local_int(bool chained)
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{
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unsigned long pending, masked;
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unsigned int intr, virq;
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pending = read_gic_vl_pend();
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masked = read_gic_vl_mask();
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bitmap_and(&pending, &pending, &masked, GIC_NUM_LOCAL_INTRS);
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for_each_set_bit(intr, &pending, GIC_NUM_LOCAL_INTRS) {
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virq = irq_linear_revmap(gic_irq_domain,
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GIC_LOCAL_TO_HWIRQ(intr));
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if (chained)
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generic_handle_irq(virq);
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else
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do_IRQ(virq);
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}
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}
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static void gic_mask_local_irq(struct irq_data *d)
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{
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int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
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write_gic_vl_rmask(BIT(intr));
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}
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static void gic_unmask_local_irq(struct irq_data *d)
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{
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int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
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write_gic_vl_smask(BIT(intr));
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}
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static struct irq_chip gic_local_irq_controller = {
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.name = "MIPS GIC Local",
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.irq_mask = gic_mask_local_irq,
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.irq_unmask = gic_unmask_local_irq,
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};
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static void gic_mask_local_irq_all_vpes(struct irq_data *d)
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{
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struct gic_all_vpes_chip_data *cd;
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unsigned long flags;
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int intr, cpu;
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intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
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cd = irq_data_get_irq_chip_data(d);
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cd->mask = false;
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spin_lock_irqsave(&gic_lock, flags);
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for_each_online_cpu(cpu) {
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write_gic_vl_other(mips_cm_vp_id(cpu));
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write_gic_vo_rmask(BIT(intr));
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}
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spin_unlock_irqrestore(&gic_lock, flags);
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}
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static void gic_unmask_local_irq_all_vpes(struct irq_data *d)
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{
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struct gic_all_vpes_chip_data *cd;
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unsigned long flags;
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int intr, cpu;
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intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
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cd = irq_data_get_irq_chip_data(d);
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cd->mask = true;
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spin_lock_irqsave(&gic_lock, flags);
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for_each_online_cpu(cpu) {
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write_gic_vl_other(mips_cm_vp_id(cpu));
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write_gic_vo_smask(BIT(intr));
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}
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spin_unlock_irqrestore(&gic_lock, flags);
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}
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static void gic_all_vpes_irq_cpu_online(struct irq_data *d)
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{
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struct gic_all_vpes_chip_data *cd;
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unsigned int intr;
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intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
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cd = irq_data_get_irq_chip_data(d);
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write_gic_vl_map(intr, cd->map);
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if (cd->mask)
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write_gic_vl_smask(BIT(intr));
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}
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static struct irq_chip gic_all_vpes_local_irq_controller = {
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.name = "MIPS GIC Local",
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.irq_mask = gic_mask_local_irq_all_vpes,
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.irq_unmask = gic_unmask_local_irq_all_vpes,
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.irq_cpu_online = gic_all_vpes_irq_cpu_online,
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};
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static void __gic_irq_dispatch(void)
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{
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gic_handle_local_int(false);
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gic_handle_shared_int(false);
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}
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static void gic_irq_dispatch(struct irq_desc *desc)
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{
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gic_handle_local_int(true);
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gic_handle_shared_int(true);
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}
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static int gic_shared_irq_domain_map(struct irq_domain *d, unsigned int virq,
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irq_hw_number_t hw, unsigned int cpu)
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{
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int intr = GIC_HWIRQ_TO_SHARED(hw);
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struct irq_data *data;
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unsigned long flags;
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data = irq_get_irq_data(virq);
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spin_lock_irqsave(&gic_lock, flags);
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write_gic_map_pin(intr, GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin);
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write_gic_map_vp(intr, BIT(mips_cm_vp_id(cpu)));
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irq_data_update_effective_affinity(data, cpumask_of(cpu));
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spin_unlock_irqrestore(&gic_lock, flags);
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return 0;
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}
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static int gic_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
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const u32 *intspec, unsigned int intsize,
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irq_hw_number_t *out_hwirq,
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unsigned int *out_type)
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{
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if (intsize != 3)
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return -EINVAL;
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if (intspec[0] == GIC_SHARED)
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*out_hwirq = GIC_SHARED_TO_HWIRQ(intspec[1]);
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else if (intspec[0] == GIC_LOCAL)
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*out_hwirq = GIC_LOCAL_TO_HWIRQ(intspec[1]);
|
|
else
|
|
return -EINVAL;
|
|
*out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int gic_irq_domain_map(struct irq_domain *d, unsigned int virq,
|
|
irq_hw_number_t hwirq)
|
|
{
|
|
struct gic_all_vpes_chip_data *cd;
|
|
unsigned long flags;
|
|
unsigned int intr;
|
|
int err, cpu;
|
|
u32 map;
|
|
|
|
if (hwirq >= GIC_SHARED_HWIRQ_BASE) {
|
|
/* verify that shared irqs don't conflict with an IPI irq */
|
|
if (test_bit(GIC_HWIRQ_TO_SHARED(hwirq), ipi_resrv))
|
|
return -EBUSY;
|
|
|
|
err = irq_domain_set_hwirq_and_chip(d, virq, hwirq,
|
|
&gic_level_irq_controller,
|
|
NULL);
|
|
if (err)
|
|
return err;
|
|
|
|
irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq)));
|
|
return gic_shared_irq_domain_map(d, virq, hwirq, 0);
|
|
}
|
|
|
|
intr = GIC_HWIRQ_TO_LOCAL(hwirq);
|
|
map = GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin;
|
|
|
|
switch (intr) {
|
|
case GIC_LOCAL_INT_TIMER:
|
|
/* CONFIG_MIPS_CMP workaround (see __gic_init) */
|
|
map = GIC_MAP_PIN_MAP_TO_PIN | timer_cpu_pin;
|
|
/* fall-through */
|
|
case GIC_LOCAL_INT_PERFCTR:
|
|
case GIC_LOCAL_INT_FDC:
|
|
/*
|
|
* HACK: These are all really percpu interrupts, but
|
|
* the rest of the MIPS kernel code does not use the
|
|
* percpu IRQ API for them.
|
|
*/
|
|
cd = &gic_all_vpes_chip_data[intr];
|
|
cd->map = map;
|
|
err = irq_domain_set_hwirq_and_chip(d, virq, hwirq,
|
|
&gic_all_vpes_local_irq_controller,
|
|
cd);
|
|
if (err)
|
|
return err;
|
|
|
|
irq_set_handler(virq, handle_percpu_irq);
|
|
break;
|
|
|
|
default:
|
|
err = irq_domain_set_hwirq_and_chip(d, virq, hwirq,
|
|
&gic_local_irq_controller,
|
|
NULL);
|
|
if (err)
|
|
return err;
|
|
|
|
irq_set_handler(virq, handle_percpu_devid_irq);
|
|
irq_set_percpu_devid(virq);
|
|
break;
|
|
}
|
|
|
|
if (!gic_local_irq_is_routable(intr))
|
|
return -EPERM;
|
|
|
|
spin_lock_irqsave(&gic_lock, flags);
|
|
for_each_online_cpu(cpu) {
|
|
write_gic_vl_other(mips_cm_vp_id(cpu));
|
|
write_gic_vo_map(intr, map);
|
|
}
|
|
spin_unlock_irqrestore(&gic_lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int gic_irq_domain_alloc(struct irq_domain *d, unsigned int virq,
|
|
unsigned int nr_irqs, void *arg)
|
|
{
|
|
struct irq_fwspec *fwspec = arg;
|
|
irq_hw_number_t hwirq;
|
|
|
|
if (fwspec->param[0] == GIC_SHARED)
|
|
hwirq = GIC_SHARED_TO_HWIRQ(fwspec->param[1]);
|
|
else
|
|
hwirq = GIC_LOCAL_TO_HWIRQ(fwspec->param[1]);
|
|
|
|
return gic_irq_domain_map(d, virq, hwirq);
|
|
}
|
|
|
|
void gic_irq_domain_free(struct irq_domain *d, unsigned int virq,
|
|
unsigned int nr_irqs)
|
|
{
|
|
}
|
|
|
|
static const struct irq_domain_ops gic_irq_domain_ops = {
|
|
.xlate = gic_irq_domain_xlate,
|
|
.alloc = gic_irq_domain_alloc,
|
|
.free = gic_irq_domain_free,
|
|
.map = gic_irq_domain_map,
|
|
};
|
|
|
|
static int gic_ipi_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
|
|
const u32 *intspec, unsigned int intsize,
|
|
irq_hw_number_t *out_hwirq,
|
|
unsigned int *out_type)
|
|
{
|
|
/*
|
|
* There's nothing to translate here. hwirq is dynamically allocated and
|
|
* the irq type is always edge triggered.
|
|
* */
|
|
*out_hwirq = 0;
|
|
*out_type = IRQ_TYPE_EDGE_RISING;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int gic_ipi_domain_alloc(struct irq_domain *d, unsigned int virq,
|
|
unsigned int nr_irqs, void *arg)
|
|
{
|
|
struct cpumask *ipimask = arg;
|
|
irq_hw_number_t hwirq, base_hwirq;
|
|
int cpu, ret, i;
|
|
|
|
base_hwirq = find_first_bit(ipi_available, gic_shared_intrs);
|
|
if (base_hwirq == gic_shared_intrs)
|
|
return -ENOMEM;
|
|
|
|
/* check that we have enough space */
|
|
for (i = base_hwirq; i < nr_irqs; i++) {
|
|
if (!test_bit(i, ipi_available))
|
|
return -EBUSY;
|
|
}
|
|
bitmap_clear(ipi_available, base_hwirq, nr_irqs);
|
|
|
|
/* map the hwirq for each cpu consecutively */
|
|
i = 0;
|
|
for_each_cpu(cpu, ipimask) {
|
|
hwirq = GIC_SHARED_TO_HWIRQ(base_hwirq + i);
|
|
|
|
ret = irq_domain_set_hwirq_and_chip(d, virq + i, hwirq,
|
|
&gic_edge_irq_controller,
|
|
NULL);
|
|
if (ret)
|
|
goto error;
|
|
|
|
ret = irq_domain_set_hwirq_and_chip(d->parent, virq + i, hwirq,
|
|
&gic_edge_irq_controller,
|
|
NULL);
|
|
if (ret)
|
|
goto error;
|
|
|
|
ret = irq_set_irq_type(virq + i, IRQ_TYPE_EDGE_RISING);
|
|
if (ret)
|
|
goto error;
|
|
|
|
ret = gic_shared_irq_domain_map(d, virq + i, hwirq, cpu);
|
|
if (ret)
|
|
goto error;
|
|
|
|
i++;
|
|
}
|
|
|
|
return 0;
|
|
error:
|
|
bitmap_set(ipi_available, base_hwirq, nr_irqs);
|
|
return ret;
|
|
}
|
|
|
|
void gic_ipi_domain_free(struct irq_domain *d, unsigned int virq,
|
|
unsigned int nr_irqs)
|
|
{
|
|
irq_hw_number_t base_hwirq;
|
|
struct irq_data *data;
|
|
|
|
data = irq_get_irq_data(virq);
|
|
if (!data)
|
|
return;
|
|
|
|
base_hwirq = GIC_HWIRQ_TO_SHARED(irqd_to_hwirq(data));
|
|
bitmap_set(ipi_available, base_hwirq, nr_irqs);
|
|
}
|
|
|
|
int gic_ipi_domain_match(struct irq_domain *d, struct device_node *node,
|
|
enum irq_domain_bus_token bus_token)
|
|
{
|
|
bool is_ipi;
|
|
|
|
switch (bus_token) {
|
|
case DOMAIN_BUS_IPI:
|
|
is_ipi = d->bus_token == bus_token;
|
|
return (!node || to_of_node(d->fwnode) == node) && is_ipi;
|
|
break;
|
|
default:
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
static const struct irq_domain_ops gic_ipi_domain_ops = {
|
|
.xlate = gic_ipi_domain_xlate,
|
|
.alloc = gic_ipi_domain_alloc,
|
|
.free = gic_ipi_domain_free,
|
|
.match = gic_ipi_domain_match,
|
|
};
|
|
|
|
static int gic_cpu_startup(unsigned int cpu)
|
|
{
|
|
/* Enable or disable EIC */
|
|
change_gic_vl_ctl(GIC_VX_CTL_EIC,
|
|
cpu_has_veic ? GIC_VX_CTL_EIC : 0);
|
|
|
|
/* Clear all local IRQ masks (ie. disable all local interrupts) */
|
|
write_gic_vl_rmask(~0);
|
|
|
|
/* Invoke irq_cpu_online callbacks to enable desired interrupts */
|
|
irq_cpu_online();
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __init gic_of_init(struct device_node *node,
|
|
struct device_node *parent)
|
|
{
|
|
unsigned int cpu_vec, i, gicconfig, v[2], num_ipis;
|
|
unsigned long reserved;
|
|
phys_addr_t gic_base;
|
|
struct resource res;
|
|
size_t gic_len;
|
|
|
|
/* Find the first available CPU vector. */
|
|
i = 0;
|
|
reserved = (C_SW0 | C_SW1) >> __ffs(C_SW0);
|
|
while (!of_property_read_u32_index(node, "mti,reserved-cpu-vectors",
|
|
i++, &cpu_vec))
|
|
reserved |= BIT(cpu_vec);
|
|
|
|
cpu_vec = find_first_zero_bit(&reserved, hweight_long(ST0_IM));
|
|
if (cpu_vec == hweight_long(ST0_IM)) {
|
|
pr_err("No CPU vectors available\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
if (of_address_to_resource(node, 0, &res)) {
|
|
/*
|
|
* Probe the CM for the GIC base address if not specified
|
|
* in the device-tree.
|
|
*/
|
|
if (mips_cm_present()) {
|
|
gic_base = read_gcr_gic_base() &
|
|
~CM_GCR_GIC_BASE_GICEN;
|
|
gic_len = 0x20000;
|
|
pr_warn("Using inherited base address %pa\n",
|
|
&gic_base);
|
|
} else {
|
|
pr_err("Failed to get memory range\n");
|
|
return -ENODEV;
|
|
}
|
|
} else {
|
|
gic_base = res.start;
|
|
gic_len = resource_size(&res);
|
|
}
|
|
|
|
if (mips_cm_present()) {
|
|
write_gcr_gic_base(gic_base | CM_GCR_GIC_BASE_GICEN);
|
|
/* Ensure GIC region is enabled before trying to access it */
|
|
__sync();
|
|
}
|
|
|
|
mips_gic_base = ioremap_nocache(gic_base, gic_len);
|
|
|
|
gicconfig = read_gic_config();
|
|
gic_shared_intrs = gicconfig & GIC_CONFIG_NUMINTERRUPTS;
|
|
gic_shared_intrs >>= __ffs(GIC_CONFIG_NUMINTERRUPTS);
|
|
gic_shared_intrs = (gic_shared_intrs + 1) * 8;
|
|
|
|
if (cpu_has_veic) {
|
|
/* Always use vector 1 in EIC mode */
|
|
gic_cpu_pin = 0;
|
|
timer_cpu_pin = gic_cpu_pin;
|
|
set_vi_handler(gic_cpu_pin + GIC_PIN_TO_VEC_OFFSET,
|
|
__gic_irq_dispatch);
|
|
} else {
|
|
gic_cpu_pin = cpu_vec - GIC_CPU_PIN_OFFSET;
|
|
irq_set_chained_handler(MIPS_CPU_IRQ_BASE + cpu_vec,
|
|
gic_irq_dispatch);
|
|
/*
|
|
* With the CMP implementation of SMP (deprecated), other CPUs
|
|
* are started by the bootloader and put into a timer based
|
|
* waiting poll loop. We must not re-route those CPU's local
|
|
* timer interrupts as the wait instruction will never finish,
|
|
* so just handle whatever CPU interrupt it is routed to by
|
|
* default.
|
|
*
|
|
* This workaround should be removed when CMP support is
|
|
* dropped.
|
|
*/
|
|
if (IS_ENABLED(CONFIG_MIPS_CMP) &&
|
|
gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER)) {
|
|
timer_cpu_pin = read_gic_vl_timer_map() & GIC_MAP_PIN_MAP;
|
|
irq_set_chained_handler(MIPS_CPU_IRQ_BASE +
|
|
GIC_CPU_PIN_OFFSET +
|
|
timer_cpu_pin,
|
|
gic_irq_dispatch);
|
|
} else {
|
|
timer_cpu_pin = gic_cpu_pin;
|
|
}
|
|
}
|
|
|
|
gic_irq_domain = irq_domain_add_simple(node, GIC_NUM_LOCAL_INTRS +
|
|
gic_shared_intrs, 0,
|
|
&gic_irq_domain_ops, NULL);
|
|
if (!gic_irq_domain) {
|
|
pr_err("Failed to add IRQ domain");
|
|
return -ENXIO;
|
|
}
|
|
|
|
gic_ipi_domain = irq_domain_add_hierarchy(gic_irq_domain,
|
|
IRQ_DOMAIN_FLAG_IPI_PER_CPU,
|
|
GIC_NUM_LOCAL_INTRS + gic_shared_intrs,
|
|
node, &gic_ipi_domain_ops, NULL);
|
|
if (!gic_ipi_domain) {
|
|
pr_err("Failed to add IPI domain");
|
|
return -ENXIO;
|
|
}
|
|
|
|
irq_domain_update_bus_token(gic_ipi_domain, DOMAIN_BUS_IPI);
|
|
|
|
if (node &&
|
|
!of_property_read_u32_array(node, "mti,reserved-ipi-vectors", v, 2)) {
|
|
bitmap_set(ipi_resrv, v[0], v[1]);
|
|
} else {
|
|
/*
|
|
* Reserve 2 interrupts per possible CPU/VP for use as IPIs,
|
|
* meeting the requirements of arch/mips SMP.
|
|
*/
|
|
num_ipis = 2 * num_possible_cpus();
|
|
bitmap_set(ipi_resrv, gic_shared_intrs - num_ipis, num_ipis);
|
|
}
|
|
|
|
bitmap_copy(ipi_available, ipi_resrv, GIC_MAX_INTRS);
|
|
|
|
board_bind_eic_interrupt = &gic_bind_eic_interrupt;
|
|
|
|
/* Setup defaults */
|
|
for (i = 0; i < gic_shared_intrs; i++) {
|
|
change_gic_pol(i, GIC_POL_ACTIVE_HIGH);
|
|
change_gic_trig(i, GIC_TRIG_LEVEL);
|
|
write_gic_rmask(i);
|
|
}
|
|
|
|
return cpuhp_setup_state(CPUHP_AP_IRQ_MIPS_GIC_STARTING,
|
|
"irqchip/mips/gic:starting",
|
|
gic_cpu_startup, NULL);
|
|
}
|
|
IRQCHIP_DECLARE(mips_gic, "mti,gic", gic_of_init);
|