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![Andre Przywara](/assets/img/avatar_default.png)
At the moment we assign our supported compatible strings to a respective instance of our sun4i_pwm_data structure, even though some of them are the same. To avoid further clutter, split out the three different combinations of features we have at the moment and name them accordingly. This should make it more obvious which compatible string to use for new SoCs. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
415 lines
10 KiB
C
415 lines
10 KiB
C
/*
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* Driver for Allwinner sun4i Pulse Width Modulation Controller
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*
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* Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
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*
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* Licensed under GPLv2.
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*/
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/jiffies.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pwm.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/time.h>
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#define PWM_CTRL_REG 0x0
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#define PWM_CH_PRD_BASE 0x4
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#define PWM_CH_PRD_OFFSET 0x4
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#define PWM_CH_PRD(ch) (PWM_CH_PRD_BASE + PWM_CH_PRD_OFFSET * (ch))
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#define PWMCH_OFFSET 15
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#define PWM_PRESCAL_MASK GENMASK(3, 0)
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#define PWM_PRESCAL_OFF 0
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#define PWM_EN BIT(4)
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#define PWM_ACT_STATE BIT(5)
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#define PWM_CLK_GATING BIT(6)
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#define PWM_MODE BIT(7)
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#define PWM_PULSE BIT(8)
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#define PWM_BYPASS BIT(9)
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#define PWM_RDY_BASE 28
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#define PWM_RDY_OFFSET 1
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#define PWM_RDY(ch) BIT(PWM_RDY_BASE + PWM_RDY_OFFSET * (ch))
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#define PWM_PRD(prd) (((prd) - 1) << 16)
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#define PWM_PRD_MASK GENMASK(15, 0)
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#define PWM_DTY_MASK GENMASK(15, 0)
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#define PWM_REG_PRD(reg) ((((reg) >> 16) & PWM_PRD_MASK) + 1)
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#define PWM_REG_DTY(reg) ((reg) & PWM_DTY_MASK)
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#define PWM_REG_PRESCAL(reg, chan) (((reg) >> ((chan) * PWMCH_OFFSET)) & PWM_PRESCAL_MASK)
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#define BIT_CH(bit, chan) ((bit) << ((chan) * PWMCH_OFFSET))
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static const u32 prescaler_table[] = {
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120,
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180,
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240,
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360,
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480,
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0,
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0,
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0,
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12000,
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24000,
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36000,
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48000,
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72000,
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0,
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0,
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0, /* Actually 1 but tested separately */
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};
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struct sun4i_pwm_data {
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bool has_prescaler_bypass;
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unsigned int npwm;
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};
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struct sun4i_pwm_chip {
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struct pwm_chip chip;
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struct clk *clk;
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void __iomem *base;
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spinlock_t ctrl_lock;
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const struct sun4i_pwm_data *data;
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unsigned long next_period[2];
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bool needs_delay[2];
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};
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static inline struct sun4i_pwm_chip *to_sun4i_pwm_chip(struct pwm_chip *chip)
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{
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return container_of(chip, struct sun4i_pwm_chip, chip);
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}
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static inline u32 sun4i_pwm_readl(struct sun4i_pwm_chip *chip,
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unsigned long offset)
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{
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return readl(chip->base + offset);
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}
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static inline void sun4i_pwm_writel(struct sun4i_pwm_chip *chip,
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u32 val, unsigned long offset)
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{
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writel(val, chip->base + offset);
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}
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static void sun4i_pwm_get_state(struct pwm_chip *chip,
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struct pwm_device *pwm,
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struct pwm_state *state)
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{
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struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
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u64 clk_rate, tmp;
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u32 val;
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unsigned int prescaler;
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clk_rate = clk_get_rate(sun4i_pwm->clk);
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val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
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if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) &&
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sun4i_pwm->data->has_prescaler_bypass)
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prescaler = 1;
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else
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prescaler = prescaler_table[PWM_REG_PRESCAL(val, pwm->hwpwm)];
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if (prescaler == 0)
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return;
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if (val & BIT_CH(PWM_ACT_STATE, pwm->hwpwm))
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state->polarity = PWM_POLARITY_NORMAL;
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else
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state->polarity = PWM_POLARITY_INVERSED;
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if ((val & BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm)) ==
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BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm))
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state->enabled = true;
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else
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state->enabled = false;
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val = sun4i_pwm_readl(sun4i_pwm, PWM_CH_PRD(pwm->hwpwm));
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tmp = prescaler * NSEC_PER_SEC * PWM_REG_DTY(val);
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state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
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tmp = prescaler * NSEC_PER_SEC * PWM_REG_PRD(val);
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state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
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}
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static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4i_pwm,
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struct pwm_state *state,
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u32 *dty, u32 *prd, unsigned int *prsclr)
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{
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u64 clk_rate, div = 0;
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unsigned int pval, prescaler = 0;
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clk_rate = clk_get_rate(sun4i_pwm->clk);
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if (sun4i_pwm->data->has_prescaler_bypass) {
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/* First, test without any prescaler when available */
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prescaler = PWM_PRESCAL_MASK;
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pval = 1;
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/*
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* When not using any prescaler, the clock period in nanoseconds
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* is not an integer so round it half up instead of
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* truncating to get less surprising values.
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*/
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div = clk_rate * state->period + NSEC_PER_SEC / 2;
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do_div(div, NSEC_PER_SEC);
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if (div - 1 > PWM_PRD_MASK)
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prescaler = 0;
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}
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if (prescaler == 0) {
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/* Go up from the first divider */
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for (prescaler = 0; prescaler < PWM_PRESCAL_MASK; prescaler++) {
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if (!prescaler_table[prescaler])
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continue;
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pval = prescaler_table[prescaler];
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div = clk_rate;
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do_div(div, pval);
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div = div * state->period;
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do_div(div, NSEC_PER_SEC);
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if (div - 1 <= PWM_PRD_MASK)
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break;
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}
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if (div - 1 > PWM_PRD_MASK)
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return -EINVAL;
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}
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*prd = div;
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div *= state->duty_cycle;
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do_div(div, state->period);
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*dty = div;
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*prsclr = prescaler;
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div = (u64)pval * NSEC_PER_SEC * *prd;
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state->period = DIV_ROUND_CLOSEST_ULL(div, clk_rate);
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div = (u64)pval * NSEC_PER_SEC * *dty;
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state->duty_cycle = DIV_ROUND_CLOSEST_ULL(div, clk_rate);
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return 0;
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}
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static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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struct pwm_state *state)
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{
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struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
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struct pwm_state cstate;
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u32 ctrl;
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int ret;
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unsigned int delay_us;
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unsigned long now;
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pwm_get_state(pwm, &cstate);
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if (!cstate.enabled) {
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ret = clk_prepare_enable(sun4i_pwm->clk);
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if (ret) {
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dev_err(chip->dev, "failed to enable PWM clock\n");
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return ret;
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}
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}
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spin_lock(&sun4i_pwm->ctrl_lock);
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ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
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if ((cstate.period != state->period) ||
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(cstate.duty_cycle != state->duty_cycle)) {
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u32 period, duty, val;
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unsigned int prescaler;
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ret = sun4i_pwm_calculate(sun4i_pwm, state,
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&duty, &period, &prescaler);
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if (ret) {
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dev_err(chip->dev, "period exceeds the maximum value\n");
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spin_unlock(&sun4i_pwm->ctrl_lock);
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if (!cstate.enabled)
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clk_disable_unprepare(sun4i_pwm->clk);
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return ret;
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}
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if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) {
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/* Prescaler changed, the clock has to be gated */
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ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
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sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
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ctrl &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm);
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ctrl |= BIT_CH(prescaler, pwm->hwpwm);
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}
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val = (duty & PWM_DTY_MASK) | PWM_PRD(period);
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sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm));
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sun4i_pwm->next_period[pwm->hwpwm] = jiffies +
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usecs_to_jiffies(cstate.period / 1000 + 1);
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sun4i_pwm->needs_delay[pwm->hwpwm] = true;
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}
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if (state->polarity != PWM_POLARITY_NORMAL)
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ctrl &= ~BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
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else
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ctrl |= BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
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ctrl |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
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if (state->enabled) {
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ctrl |= BIT_CH(PWM_EN, pwm->hwpwm);
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} else if (!sun4i_pwm->needs_delay[pwm->hwpwm]) {
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ctrl &= ~BIT_CH(PWM_EN, pwm->hwpwm);
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ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
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}
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sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
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spin_unlock(&sun4i_pwm->ctrl_lock);
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if (state->enabled)
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return 0;
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if (!sun4i_pwm->needs_delay[pwm->hwpwm]) {
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clk_disable_unprepare(sun4i_pwm->clk);
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return 0;
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}
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/* We need a full period to elapse before disabling the channel. */
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now = jiffies;
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if (sun4i_pwm->needs_delay[pwm->hwpwm] &&
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time_before(now, sun4i_pwm->next_period[pwm->hwpwm])) {
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delay_us = jiffies_to_usecs(sun4i_pwm->next_period[pwm->hwpwm] -
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now);
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if ((delay_us / 500) > MAX_UDELAY_MS)
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msleep(delay_us / 1000 + 1);
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else
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usleep_range(delay_us, delay_us * 2);
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}
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sun4i_pwm->needs_delay[pwm->hwpwm] = false;
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spin_lock(&sun4i_pwm->ctrl_lock);
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ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
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ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
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ctrl &= ~BIT_CH(PWM_EN, pwm->hwpwm);
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sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
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spin_unlock(&sun4i_pwm->ctrl_lock);
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clk_disable_unprepare(sun4i_pwm->clk);
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return 0;
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}
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static const struct pwm_ops sun4i_pwm_ops = {
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.apply = sun4i_pwm_apply,
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.get_state = sun4i_pwm_get_state,
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.owner = THIS_MODULE,
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};
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static const struct sun4i_pwm_data sun4i_pwm_dual_nobypass = {
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.has_prescaler_bypass = false,
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.npwm = 2,
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};
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static const struct sun4i_pwm_data sun4i_pwm_dual_bypass = {
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.has_prescaler_bypass = true,
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.npwm = 2,
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};
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static const struct sun4i_pwm_data sun4i_pwm_single_bypass = {
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.has_prescaler_bypass = true,
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.npwm = 1,
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};
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static const struct of_device_id sun4i_pwm_dt_ids[] = {
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{
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.compatible = "allwinner,sun4i-a10-pwm",
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.data = &sun4i_pwm_dual_nobypass,
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}, {
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.compatible = "allwinner,sun5i-a10s-pwm",
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.data = &sun4i_pwm_dual_bypass,
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}, {
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.compatible = "allwinner,sun5i-a13-pwm",
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.data = &sun4i_pwm_single_bypass,
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}, {
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.compatible = "allwinner,sun7i-a20-pwm",
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.data = &sun4i_pwm_dual_bypass,
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}, {
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.compatible = "allwinner,sun8i-h3-pwm",
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.data = &sun4i_pwm_single_bypass,
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}, {
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/* sentinel */
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},
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};
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MODULE_DEVICE_TABLE(of, sun4i_pwm_dt_ids);
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static int sun4i_pwm_probe(struct platform_device *pdev)
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{
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struct sun4i_pwm_chip *pwm;
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struct resource *res;
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int ret;
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pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
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if (!pwm)
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return -ENOMEM;
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pwm->data = of_device_get_match_data(&pdev->dev);
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if (!pwm->data)
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return -ENODEV;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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pwm->base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(pwm->base))
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return PTR_ERR(pwm->base);
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pwm->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(pwm->clk))
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return PTR_ERR(pwm->clk);
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pwm->chip.dev = &pdev->dev;
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pwm->chip.ops = &sun4i_pwm_ops;
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pwm->chip.base = -1;
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pwm->chip.npwm = pwm->data->npwm;
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pwm->chip.of_xlate = of_pwm_xlate_with_flags;
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pwm->chip.of_pwm_n_cells = 3;
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spin_lock_init(&pwm->ctrl_lock);
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ret = pwmchip_add(&pwm->chip);
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if (ret < 0) {
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dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
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return ret;
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}
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platform_set_drvdata(pdev, pwm);
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return 0;
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}
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static int sun4i_pwm_remove(struct platform_device *pdev)
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{
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struct sun4i_pwm_chip *pwm = platform_get_drvdata(pdev);
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return pwmchip_remove(&pwm->chip);
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}
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static struct platform_driver sun4i_pwm_driver = {
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.driver = {
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.name = "sun4i-pwm",
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.of_match_table = sun4i_pwm_dt_ids,
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},
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.probe = sun4i_pwm_probe,
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.remove = sun4i_pwm_remove,
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};
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module_platform_driver(sun4i_pwm_driver);
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MODULE_ALIAS("platform:sun4i-pwm");
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MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@free-electrons.com>");
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MODULE_DESCRIPTION("Allwinner sun4i PWM driver");
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MODULE_LICENSE("GPL v2");
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