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![Uwe Kleine-König](/assets/img/avatar_default.png)
The function returned zero unconditionally, so the function returning an int is something between useless and irritating. With the goal to make platform drivers' remove function return void, it's helpful to convert the function accordingly. This converts several drivers to the new .remove_new callback that was introduced to smoothen the platform driver conversion. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Acked-by: Serge Semin <fancer.lancer@gmail.com> Reviewed-by: Sergey Shtylyov <s.shtylyov@omp.ru> Signed-off-by: Damien Le Moal <dlemoal@kernel.org>
252 lines
6.2 KiB
C
252 lines
6.2 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* DaVinci DA850 AHCI SATA platform driver
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pm.h>
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#include <linux/device.h>
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#include <linux/platform_device.h>
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#include <linux/libata.h>
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#include <linux/ahci_platform.h>
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#include "ahci.h"
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#define DRV_NAME "ahci_da850"
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#define HARDRESET_RETRIES 5
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/* SATA PHY Control Register offset from AHCI base */
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#define SATA_P0PHYCR_REG 0x178
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#define SATA_PHY_MPY(x) ((x) << 0)
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#define SATA_PHY_LOS(x) ((x) << 6)
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#define SATA_PHY_RXCDR(x) ((x) << 10)
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#define SATA_PHY_RXEQ(x) ((x) << 13)
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#define SATA_PHY_TXSWING(x) ((x) << 19)
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#define SATA_PHY_ENPLL(x) ((x) << 31)
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static void da850_sata_init(struct device *dev, void __iomem *pwrdn_reg,
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void __iomem *ahci_base, u32 mpy)
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{
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unsigned int val;
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/* Enable SATA clock receiver */
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val = readl(pwrdn_reg);
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val &= ~BIT(0);
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writel(val, pwrdn_reg);
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val = SATA_PHY_MPY(mpy) | SATA_PHY_LOS(1) | SATA_PHY_RXCDR(4) |
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SATA_PHY_RXEQ(1) | SATA_PHY_TXSWING(3) | SATA_PHY_ENPLL(1);
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writel(val, ahci_base + SATA_P0PHYCR_REG);
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}
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static u32 ahci_da850_calculate_mpy(unsigned long refclk_rate)
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{
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u32 pll_output = 1500000000, needed;
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/*
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* We need to determine the value of the multiplier (MPY) bits.
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* In order to include the 12.5 multiplier we need to first divide
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* the refclk rate by ten.
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*
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* __div64_32() turned out to be unreliable, sometimes returning
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* false results.
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*/
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WARN((refclk_rate % 10) != 0, "refclk must be divisible by 10");
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needed = pll_output / (refclk_rate / 10);
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/*
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* What we have now is (multiplier * 10).
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*
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* Let's determine the actual register value we need to write.
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*/
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switch (needed) {
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case 50:
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return 0x1;
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case 60:
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return 0x2;
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case 80:
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return 0x4;
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case 100:
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return 0x5;
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case 120:
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return 0x6;
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case 125:
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return 0x7;
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case 150:
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return 0x8;
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case 200:
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return 0x9;
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case 250:
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return 0xa;
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default:
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/*
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* We should have divided evenly - if not, return an invalid
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* value.
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*/
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return 0;
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}
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}
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static int ahci_da850_softreset(struct ata_link *link,
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unsigned int *class, unsigned long deadline)
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{
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int pmp, ret;
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pmp = sata_srst_pmp(link);
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/*
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* There's an issue with the SATA controller on da850 SoCs: if we
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* enable Port Multiplier support, but the drive is connected directly
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* to the board, it can't be detected. As a workaround: if PMP is
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* enabled, we first call ahci_do_softreset() and pass it the result of
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* sata_srst_pmp(). If this call fails, we retry with pmp = 0.
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*/
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ret = ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
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if (pmp && ret == -EBUSY)
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return ahci_do_softreset(link, class, 0,
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deadline, ahci_check_ready);
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return ret;
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}
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static int ahci_da850_hardreset(struct ata_link *link,
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unsigned int *class, unsigned long deadline)
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{
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int ret, retry = HARDRESET_RETRIES;
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bool online;
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/*
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* In order to correctly service the LCD controller of the da850 SoC,
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* we increased the PLL0 frequency to 456MHz from the default 300MHz.
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*
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* This made the SATA controller unstable and the hardreset operation
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* does not always succeed the first time. Before really giving up to
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* bring up the link, retry the reset a couple times.
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*/
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do {
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ret = ahci_do_hardreset(link, class, deadline, &online);
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if (online)
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return ret;
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} while (retry--);
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return ret;
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}
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static struct ata_port_operations ahci_da850_port_ops = {
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.inherits = &ahci_platform_ops,
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.softreset = ahci_da850_softreset,
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/*
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* No need to override .pmp_softreset - it's only used for actual
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* PMP-enabled ports.
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*/
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.hardreset = ahci_da850_hardreset,
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.pmp_hardreset = ahci_da850_hardreset,
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};
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static const struct ata_port_info ahci_da850_port_info = {
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.flags = AHCI_FLAG_COMMON,
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.pio_mask = ATA_PIO4,
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.udma_mask = ATA_UDMA6,
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.port_ops = &ahci_da850_port_ops,
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};
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static const struct scsi_host_template ahci_platform_sht = {
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AHCI_SHT(DRV_NAME),
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};
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static int ahci_da850_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct ahci_host_priv *hpriv;
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void __iomem *pwrdn_reg;
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struct resource *res;
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u32 mpy;
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int rc;
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hpriv = ahci_platform_get_resources(pdev, 0);
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if (IS_ERR(hpriv))
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return PTR_ERR(hpriv);
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/*
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* Internally ahci_platform_get_resources() calls the bulk clocks
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* get method or falls back to using a single clk_get_optional().
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* This AHCI SATA controller uses two clocks: functional clock
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* with "fck" connection id and external reference clock with
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* "refclk" id. If we haven't got all of them re-try the clocks
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* getting procedure with the explicitly specified ids.
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*/
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if (hpriv->n_clks < 2) {
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hpriv->clks = devm_kcalloc(dev, 2, sizeof(*hpriv->clks), GFP_KERNEL);
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if (!hpriv->clks)
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return -ENOMEM;
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hpriv->clks[0].id = "fck";
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hpriv->clks[1].id = "refclk";
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hpriv->n_clks = 2;
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rc = devm_clk_bulk_get(dev, hpriv->n_clks, hpriv->clks);
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if (rc)
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return rc;
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}
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mpy = ahci_da850_calculate_mpy(clk_get_rate(hpriv->clks[1].clk));
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if (mpy == 0) {
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dev_err(dev, "invalid REFCLK multiplier value: 0x%x", mpy);
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return -EINVAL;
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}
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rc = ahci_platform_enable_resources(hpriv);
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if (rc)
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return rc;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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if (!res) {
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rc = -ENODEV;
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goto disable_resources;
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}
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pwrdn_reg = devm_ioremap(dev, res->start, resource_size(res));
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if (!pwrdn_reg) {
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rc = -ENOMEM;
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goto disable_resources;
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}
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da850_sata_init(dev, pwrdn_reg, hpriv->mmio, mpy);
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rc = ahci_platform_init_host(pdev, hpriv, &ahci_da850_port_info,
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&ahci_platform_sht);
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if (rc)
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goto disable_resources;
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return 0;
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disable_resources:
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ahci_platform_disable_resources(hpriv);
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return rc;
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}
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static SIMPLE_DEV_PM_OPS(ahci_da850_pm_ops, ahci_platform_suspend,
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ahci_platform_resume);
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static const struct of_device_id ahci_da850_of_match[] = {
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{ .compatible = "ti,da850-ahci", },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, ahci_da850_of_match);
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static struct platform_driver ahci_da850_driver = {
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.probe = ahci_da850_probe,
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.remove_new = ata_platform_remove_one,
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.driver = {
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.name = DRV_NAME,
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.of_match_table = ahci_da850_of_match,
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.pm = &ahci_da850_pm_ops,
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},
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};
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module_platform_driver(ahci_da850_driver);
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MODULE_DESCRIPTION("DaVinci DA850 AHCI SATA platform driver");
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MODULE_AUTHOR("Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>");
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MODULE_LICENSE("GPL");
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