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![Maxime Ripard](/assets/img/avatar_default.png)
The lochnagar clocks implement a mux with a set_parent hook, but doesn't provide a determine_rate implementation. This is a bit odd, since set_parent() is there to, as its name implies, change the parent of a clock. However, the most likely candidates to trigger that parent change are either the assigned-clock-parents device tree property or a call to clk_set_rate(), with determine_rate() figuring out which parent is the best suited for a given rate. The other trigger would be a call to clk_set_parent(), but it's far less used, and it doesn't look like there's any obvious user for that clock. Since there's no upstream device tree using that driver, it's a bit hard to tell if it uses the assigned-clock properties. The binding and its example uses them though, so it's likely that the author intent was to force the parent through the device tree and prevent any reparenting but through an explicit call to clk_set_parent(). This case is equivalent to setting the determine_rate implementation to clk_hw_determine_rate_no_reparent(). Indeed, if no determine_rate implementation is provided, clk_round_rate() (through clk_core_round_rate_nolock()) will call itself on the parent if CLK_SET_RATE_PARENT is set, and will not change the clock rate otherwise. Cc: Charles Keepax <ckeepax@opensource.cirrus.com> Cc: Richard Fitzgerald <rf@opensource.cirrus.com> Cc: patches@opensource.cirrus.com Tested-by: Charles Keepax <ckeepax@opensource.cirrus.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20221018-clk-range-checks-fixes-v4-17-971d5077e7d2@cerno.tech | Reported-by: kernel test robot <lkp@intel.com>: | Reported-by: kernel test robot <lkp@intel.com>: Signed-off-by: Stephen Boyd <sboyd@kernel.org>
304 lines
7.7 KiB
C
304 lines
7.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Lochnagar clock control
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*
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* Copyright (c) 2017-2018 Cirrus Logic, Inc. and
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* Cirrus Logic International Semiconductor Ltd.
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*
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* Author: Charles Keepax <ckeepax@opensource.cirrus.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/device.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/mfd/lochnagar1_regs.h>
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#include <linux/mfd/lochnagar2_regs.h>
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#include <dt-bindings/clock/lochnagar.h>
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#define LOCHNAGAR_NUM_CLOCKS (LOCHNAGAR_SPDIF_CLKOUT + 1)
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struct lochnagar_clk {
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const char * const name;
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struct clk_hw hw;
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struct lochnagar_clk_priv *priv;
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u16 cfg_reg;
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u16 ena_mask;
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u16 src_reg;
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u16 src_mask;
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};
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struct lochnagar_clk_priv {
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struct device *dev;
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struct regmap *regmap;
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struct lochnagar_clk lclks[LOCHNAGAR_NUM_CLOCKS];
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};
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#define LN_PARENT(NAME) { .name = NAME, .fw_name = NAME }
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static const struct clk_parent_data lochnagar1_clk_parents[] = {
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LN_PARENT("ln-none"),
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LN_PARENT("ln-spdif-mclk"),
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LN_PARENT("ln-psia1-mclk"),
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LN_PARENT("ln-psia2-mclk"),
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LN_PARENT("ln-cdc-clkout"),
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LN_PARENT("ln-dsp-clkout"),
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LN_PARENT("ln-pmic-32k"),
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LN_PARENT("ln-gf-mclk1"),
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LN_PARENT("ln-gf-mclk3"),
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LN_PARENT("ln-gf-mclk2"),
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LN_PARENT("ln-gf-mclk4"),
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};
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static const struct clk_parent_data lochnagar2_clk_parents[] = {
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LN_PARENT("ln-none"),
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LN_PARENT("ln-cdc-clkout"),
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LN_PARENT("ln-dsp-clkout"),
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LN_PARENT("ln-pmic-32k"),
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LN_PARENT("ln-spdif-mclk"),
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LN_PARENT("ln-clk-12m"),
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LN_PARENT("ln-clk-11m"),
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LN_PARENT("ln-clk-24m"),
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LN_PARENT("ln-clk-22m"),
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LN_PARENT("ln-clk-8m"),
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LN_PARENT("ln-usb-clk-24m"),
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LN_PARENT("ln-gf-mclk1"),
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LN_PARENT("ln-gf-mclk3"),
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LN_PARENT("ln-gf-mclk2"),
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LN_PARENT("ln-psia1-mclk"),
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LN_PARENT("ln-psia2-mclk"),
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LN_PARENT("ln-spdif-clkout"),
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LN_PARENT("ln-adat-mclk"),
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LN_PARENT("ln-usb-clk-12m"),
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};
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#define LN1_CLK(ID, NAME, REG) \
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[LOCHNAGAR_##ID] = { \
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.name = NAME, \
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.cfg_reg = LOCHNAGAR1_##REG, \
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.ena_mask = LOCHNAGAR1_##ID##_ENA_MASK, \
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.src_reg = LOCHNAGAR1_##ID##_SEL, \
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.src_mask = LOCHNAGAR1_SRC_MASK, \
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}
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#define LN2_CLK(ID, NAME) \
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[LOCHNAGAR_##ID] = { \
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.name = NAME, \
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.cfg_reg = LOCHNAGAR2_##ID##_CTRL, \
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.src_reg = LOCHNAGAR2_##ID##_CTRL, \
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.ena_mask = LOCHNAGAR2_CLK_ENA_MASK, \
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.src_mask = LOCHNAGAR2_CLK_SRC_MASK, \
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}
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static const struct lochnagar_clk lochnagar1_clks[LOCHNAGAR_NUM_CLOCKS] = {
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LN1_CLK(CDC_MCLK1, "ln-cdc-mclk1", CDC_AIF_CTRL2),
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LN1_CLK(CDC_MCLK2, "ln-cdc-mclk2", CDC_AIF_CTRL2),
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LN1_CLK(DSP_CLKIN, "ln-dsp-clkin", DSP_AIF),
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LN1_CLK(GF_CLKOUT1, "ln-gf-clkout1", GF_AIF1),
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};
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static const struct lochnagar_clk lochnagar2_clks[LOCHNAGAR_NUM_CLOCKS] = {
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LN2_CLK(CDC_MCLK1, "ln-cdc-mclk1"),
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LN2_CLK(CDC_MCLK2, "ln-cdc-mclk2"),
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LN2_CLK(DSP_CLKIN, "ln-dsp-clkin"),
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LN2_CLK(GF_CLKOUT1, "ln-gf-clkout1"),
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LN2_CLK(GF_CLKOUT2, "ln-gf-clkout2"),
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LN2_CLK(PSIA1_MCLK, "ln-psia1-mclk"),
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LN2_CLK(PSIA2_MCLK, "ln-psia2-mclk"),
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LN2_CLK(SPDIF_MCLK, "ln-spdif-mclk"),
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LN2_CLK(ADAT_MCLK, "ln-adat-mclk"),
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LN2_CLK(SOUNDCARD_MCLK, "ln-soundcard-mclk"),
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};
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struct lochnagar_config {
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const struct clk_parent_data *parents;
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int nparents;
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const struct lochnagar_clk *clks;
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};
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static const struct lochnagar_config lochnagar1_conf = {
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.parents = lochnagar1_clk_parents,
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.nparents = ARRAY_SIZE(lochnagar1_clk_parents),
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.clks = lochnagar1_clks,
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};
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static const struct lochnagar_config lochnagar2_conf = {
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.parents = lochnagar2_clk_parents,
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.nparents = ARRAY_SIZE(lochnagar2_clk_parents),
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.clks = lochnagar2_clks,
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};
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static inline struct lochnagar_clk *lochnagar_hw_to_lclk(struct clk_hw *hw)
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{
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return container_of(hw, struct lochnagar_clk, hw);
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}
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static int lochnagar_clk_prepare(struct clk_hw *hw)
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{
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struct lochnagar_clk *lclk = lochnagar_hw_to_lclk(hw);
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struct lochnagar_clk_priv *priv = lclk->priv;
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struct regmap *regmap = priv->regmap;
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int ret;
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ret = regmap_update_bits(regmap, lclk->cfg_reg,
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lclk->ena_mask, lclk->ena_mask);
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if (ret < 0)
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dev_dbg(priv->dev, "Failed to prepare %s: %d\n",
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lclk->name, ret);
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return ret;
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}
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static void lochnagar_clk_unprepare(struct clk_hw *hw)
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{
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struct lochnagar_clk *lclk = lochnagar_hw_to_lclk(hw);
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struct lochnagar_clk_priv *priv = lclk->priv;
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struct regmap *regmap = priv->regmap;
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int ret;
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ret = regmap_update_bits(regmap, lclk->cfg_reg, lclk->ena_mask, 0);
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if (ret < 0)
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dev_dbg(priv->dev, "Failed to unprepare %s: %d\n",
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lclk->name, ret);
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}
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static int lochnagar_clk_set_parent(struct clk_hw *hw, u8 index)
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{
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struct lochnagar_clk *lclk = lochnagar_hw_to_lclk(hw);
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struct lochnagar_clk_priv *priv = lclk->priv;
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struct regmap *regmap = priv->regmap;
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int ret;
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ret = regmap_update_bits(regmap, lclk->src_reg, lclk->src_mask, index);
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if (ret < 0)
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dev_dbg(priv->dev, "Failed to reparent %s: %d\n",
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lclk->name, ret);
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return ret;
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}
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static u8 lochnagar_clk_get_parent(struct clk_hw *hw)
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{
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struct lochnagar_clk *lclk = lochnagar_hw_to_lclk(hw);
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struct lochnagar_clk_priv *priv = lclk->priv;
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struct regmap *regmap = priv->regmap;
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unsigned int val;
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int ret;
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ret = regmap_read(regmap, lclk->src_reg, &val);
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if (ret < 0) {
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dev_dbg(priv->dev, "Failed to read parent of %s: %d\n",
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lclk->name, ret);
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return clk_hw_get_num_parents(hw);
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}
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val &= lclk->src_mask;
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return val;
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}
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static const struct clk_ops lochnagar_clk_ops = {
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.prepare = lochnagar_clk_prepare,
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.unprepare = lochnagar_clk_unprepare,
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.determine_rate = clk_hw_determine_rate_no_reparent,
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.set_parent = lochnagar_clk_set_parent,
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.get_parent = lochnagar_clk_get_parent,
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};
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static struct clk_hw *
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lochnagar_of_clk_hw_get(struct of_phandle_args *clkspec, void *data)
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{
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struct lochnagar_clk_priv *priv = data;
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unsigned int idx = clkspec->args[0];
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if (idx >= ARRAY_SIZE(priv->lclks)) {
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dev_err(priv->dev, "Invalid index %u\n", idx);
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return ERR_PTR(-EINVAL);
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}
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return &priv->lclks[idx].hw;
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}
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static const struct of_device_id lochnagar_of_match[] = {
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{ .compatible = "cirrus,lochnagar1-clk", .data = &lochnagar1_conf },
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{ .compatible = "cirrus,lochnagar2-clk", .data = &lochnagar2_conf },
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{}
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};
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MODULE_DEVICE_TABLE(of, lochnagar_of_match);
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static int lochnagar_clk_probe(struct platform_device *pdev)
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{
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struct clk_init_data clk_init = {
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.ops = &lochnagar_clk_ops,
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};
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struct device *dev = &pdev->dev;
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struct lochnagar_clk_priv *priv;
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const struct of_device_id *of_id;
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struct lochnagar_clk *lclk;
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struct lochnagar_config *conf;
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int ret, i;
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of_id = of_match_device(lochnagar_of_match, dev);
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if (!of_id)
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return -EINVAL;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->dev = dev;
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priv->regmap = dev_get_regmap(dev->parent, NULL);
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conf = (struct lochnagar_config *)of_id->data;
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memcpy(priv->lclks, conf->clks, sizeof(priv->lclks));
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clk_init.parent_data = conf->parents;
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clk_init.num_parents = conf->nparents;
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for (i = 0; i < ARRAY_SIZE(priv->lclks); i++) {
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lclk = &priv->lclks[i];
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if (!lclk->name)
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continue;
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clk_init.name = lclk->name;
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lclk->priv = priv;
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lclk->hw.init = &clk_init;
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ret = devm_clk_hw_register(dev, &lclk->hw);
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if (ret) {
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dev_err(dev, "Failed to register %s: %d\n",
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lclk->name, ret);
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return ret;
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}
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}
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ret = devm_of_clk_add_hw_provider(dev, lochnagar_of_clk_hw_get, priv);
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if (ret < 0)
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dev_err(dev, "Failed to register provider: %d\n", ret);
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return ret;
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}
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static struct platform_driver lochnagar_clk_driver = {
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.driver = {
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.name = "lochnagar-clk",
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.of_match_table = lochnagar_of_match,
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},
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.probe = lochnagar_clk_probe,
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};
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module_platform_driver(lochnagar_clk_driver);
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MODULE_AUTHOR("Charles Keepax <ckeepax@opensource.cirrus.com>");
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MODULE_DESCRIPTION("Clock driver for Cirrus Logic Lochnagar Board");
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MODULE_LICENSE("GPL v2");
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