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![Yangtao Li](/assets/img/avatar_default.png)
The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is (mostly) ignored and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new() which already returns void. Trivially convert this driver from always returning zero in the remove callback to the void returning variant. Cc: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Yangtao Li <frank.li@vivo.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
195 lines
5.3 KiB
C
195 lines
5.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2019 NXP
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*/
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#include <linux/clk.h>
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#include <linux/cpu.h>
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#include <linux/cpufreq.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/nvmem-consumer.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_opp.h>
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#include <linux/regulator/consumer.h>
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#include <linux/slab.h>
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#include "cpufreq-dt.h"
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#define OCOTP_CFG3_SPEED_GRADE_SHIFT 8
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#define OCOTP_CFG3_SPEED_GRADE_MASK (0x3 << 8)
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#define IMX8MN_OCOTP_CFG3_SPEED_GRADE_MASK (0xf << 8)
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#define OCOTP_CFG3_MKT_SEGMENT_SHIFT 6
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#define OCOTP_CFG3_MKT_SEGMENT_MASK (0x3 << 6)
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#define IMX8MP_OCOTP_CFG3_MKT_SEGMENT_SHIFT 5
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#define IMX8MP_OCOTP_CFG3_MKT_SEGMENT_MASK (0x3 << 5)
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#define IMX7ULP_MAX_RUN_FREQ 528000
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/* cpufreq-dt device registered by imx-cpufreq-dt */
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static struct platform_device *cpufreq_dt_pdev;
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static struct device *cpu_dev;
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static int cpufreq_opp_token;
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enum IMX7ULP_CPUFREQ_CLKS {
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ARM,
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CORE,
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SCS_SEL,
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HSRUN_CORE,
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HSRUN_SCS_SEL,
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FIRC,
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};
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static struct clk_bulk_data imx7ulp_clks[] = {
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{ .id = "arm" },
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{ .id = "core" },
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{ .id = "scs_sel" },
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{ .id = "hsrun_core" },
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{ .id = "hsrun_scs_sel" },
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{ .id = "firc" },
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};
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static unsigned int imx7ulp_get_intermediate(struct cpufreq_policy *policy,
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unsigned int index)
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{
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return clk_get_rate(imx7ulp_clks[FIRC].clk);
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}
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static int imx7ulp_target_intermediate(struct cpufreq_policy *policy,
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unsigned int index)
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{
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unsigned int newfreq = policy->freq_table[index].frequency;
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clk_set_parent(imx7ulp_clks[SCS_SEL].clk, imx7ulp_clks[FIRC].clk);
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clk_set_parent(imx7ulp_clks[HSRUN_SCS_SEL].clk, imx7ulp_clks[FIRC].clk);
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if (newfreq > IMX7ULP_MAX_RUN_FREQ)
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clk_set_parent(imx7ulp_clks[ARM].clk,
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imx7ulp_clks[HSRUN_CORE].clk);
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else
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clk_set_parent(imx7ulp_clks[ARM].clk, imx7ulp_clks[CORE].clk);
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return 0;
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}
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static struct cpufreq_dt_platform_data imx7ulp_data = {
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.target_intermediate = imx7ulp_target_intermediate,
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.get_intermediate = imx7ulp_get_intermediate,
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};
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static int imx_cpufreq_dt_probe(struct platform_device *pdev)
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{
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struct platform_device *dt_pdev;
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u32 cell_value, supported_hw[2];
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int speed_grade, mkt_segment;
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int ret;
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cpu_dev = get_cpu_device(0);
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if (!of_property_present(cpu_dev->of_node, "cpu-supply"))
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return -ENODEV;
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if (of_machine_is_compatible("fsl,imx7ulp")) {
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ret = clk_bulk_get(cpu_dev, ARRAY_SIZE(imx7ulp_clks),
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imx7ulp_clks);
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if (ret)
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return ret;
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dt_pdev = platform_device_register_data(NULL, "cpufreq-dt",
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-1, &imx7ulp_data,
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sizeof(imx7ulp_data));
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if (IS_ERR(dt_pdev)) {
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clk_bulk_put(ARRAY_SIZE(imx7ulp_clks), imx7ulp_clks);
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ret = PTR_ERR(dt_pdev);
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dev_err(&pdev->dev, "Failed to register cpufreq-dt: %d\n", ret);
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return ret;
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}
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cpufreq_dt_pdev = dt_pdev;
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return 0;
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}
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ret = nvmem_cell_read_u32(cpu_dev, "speed_grade", &cell_value);
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if (ret)
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return ret;
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if (of_machine_is_compatible("fsl,imx8mn") ||
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of_machine_is_compatible("fsl,imx8mp"))
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speed_grade = (cell_value & IMX8MN_OCOTP_CFG3_SPEED_GRADE_MASK)
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>> OCOTP_CFG3_SPEED_GRADE_SHIFT;
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else
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speed_grade = (cell_value & OCOTP_CFG3_SPEED_GRADE_MASK)
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>> OCOTP_CFG3_SPEED_GRADE_SHIFT;
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if (of_machine_is_compatible("fsl,imx8mp"))
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mkt_segment = (cell_value & IMX8MP_OCOTP_CFG3_MKT_SEGMENT_MASK)
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>> IMX8MP_OCOTP_CFG3_MKT_SEGMENT_SHIFT;
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else
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mkt_segment = (cell_value & OCOTP_CFG3_MKT_SEGMENT_MASK)
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>> OCOTP_CFG3_MKT_SEGMENT_SHIFT;
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/*
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* Early samples without fuses written report "0 0" which may NOT
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* match any OPP defined in DT. So clamp to minimum OPP defined in
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* DT to avoid warning for "no OPPs".
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*
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* Applies to i.MX8M series SoCs.
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*/
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if (mkt_segment == 0 && speed_grade == 0) {
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if (of_machine_is_compatible("fsl,imx8mm") ||
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of_machine_is_compatible("fsl,imx8mq"))
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speed_grade = 1;
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if (of_machine_is_compatible("fsl,imx8mn") ||
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of_machine_is_compatible("fsl,imx8mp"))
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speed_grade = 0xb;
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}
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supported_hw[0] = BIT(speed_grade);
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supported_hw[1] = BIT(mkt_segment);
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dev_info(&pdev->dev, "cpu speed grade %d mkt segment %d supported-hw %#x %#x\n",
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speed_grade, mkt_segment, supported_hw[0], supported_hw[1]);
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cpufreq_opp_token = dev_pm_opp_set_supported_hw(cpu_dev, supported_hw, 2);
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if (cpufreq_opp_token < 0) {
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ret = cpufreq_opp_token;
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dev_err(&pdev->dev, "Failed to set supported opp: %d\n", ret);
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return ret;
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}
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cpufreq_dt_pdev = platform_device_register_data(
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&pdev->dev, "cpufreq-dt", -1, NULL, 0);
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if (IS_ERR(cpufreq_dt_pdev)) {
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dev_pm_opp_put_supported_hw(cpufreq_opp_token);
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ret = PTR_ERR(cpufreq_dt_pdev);
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dev_err(&pdev->dev, "Failed to register cpufreq-dt: %d\n", ret);
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return ret;
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}
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return 0;
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}
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static void imx_cpufreq_dt_remove(struct platform_device *pdev)
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{
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platform_device_unregister(cpufreq_dt_pdev);
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if (!of_machine_is_compatible("fsl,imx7ulp"))
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dev_pm_opp_put_supported_hw(cpufreq_opp_token);
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else
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clk_bulk_put(ARRAY_SIZE(imx7ulp_clks), imx7ulp_clks);
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}
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static struct platform_driver imx_cpufreq_dt_driver = {
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.probe = imx_cpufreq_dt_probe,
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.remove_new = imx_cpufreq_dt_remove,
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.driver = {
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.name = "imx-cpufreq-dt",
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},
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};
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module_platform_driver(imx_cpufreq_dt_driver);
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MODULE_ALIAS("platform:imx-cpufreq-dt");
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MODULE_DESCRIPTION("Freescale i.MX cpufreq speed grading driver");
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MODULE_LICENSE("GPL v2");
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