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![Kees Cook](/assets/img/avatar_default.png)
Prepare for the coming implementation by GCC and Clang of the __counted_by attribute. Flexible array members annotated with __counted_by can have their accesses bounds-checked at run-time checking via CONFIG_UBSAN_BOUNDS (for array indexing) and CONFIG_FORTIFY_SOURCE (for strcpy/memcpy-family functions). As found with Coccinelle[1], add __counted_by for struct cxl_cxims_data. Additionally, since the element count member must be set before accessing the annotated flexible array member, move its initialization earlier. [1] https://github.com/kees/kernel-tools/blob/trunk/coccinelle/examples/counted_by.cocci Cc: Davidlohr Bueso <dave@stgolabs.net> Cc: Jonathan Cameron <jonathan.cameron@huawei.com> Cc: Dave Jiang <dave.jiang@intel.com> Cc: Alison Schofield <alison.schofield@intel.com> Cc: Vishal Verma <vishal.l.verma@intel.com> Cc: Ira Weiny <ira.weiny@intel.com> Cc: Dan Williams <dan.j.williams@intel.com> Cc: linux-cxl@vger.kernel.org Signed-off-by: Kees Cook <keescook@chromium.org> Reviewed-by: Vishal Verma <vishal.l.verma@intel.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/20230922175319.work.096-kees@kernel.org Signed-off-by: Dan Williams <dan.j.williams@intel.com>
764 lines
18 KiB
C
764 lines
18 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright(c) 2021 Intel Corporation. All rights reserved. */
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#include <linux/platform_device.h>
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/kernel.h>
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#include <linux/acpi.h>
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#include <linux/pci.h>
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#include <asm/div64.h>
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#include "cxlpci.h"
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#include "cxl.h"
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#define CXL_RCRB_SIZE SZ_8K
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struct cxl_cxims_data {
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int nr_maps;
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u64 xormaps[] __counted_by(nr_maps);
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};
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/*
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* Find a targets entry (n) in the host bridge interleave list.
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* CXL Specification 3.0 Table 9-22
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*/
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static int cxl_xor_calc_n(u64 hpa, struct cxl_cxims_data *cximsd, int iw,
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int ig)
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{
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int i = 0, n = 0;
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u8 eiw;
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/* IW: 2,4,6,8,12,16 begin building 'n' using xormaps */
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if (iw != 3) {
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for (i = 0; i < cximsd->nr_maps; i++)
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n |= (hweight64(hpa & cximsd->xormaps[i]) & 1) << i;
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}
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/* IW: 3,6,12 add a modulo calculation to 'n' */
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if (!is_power_of_2(iw)) {
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if (ways_to_eiw(iw, &eiw))
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return -1;
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hpa &= GENMASK_ULL(51, eiw + ig);
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n |= do_div(hpa, 3) << i;
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}
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return n;
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}
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static struct cxl_dport *cxl_hb_xor(struct cxl_root_decoder *cxlrd, int pos)
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{
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struct cxl_cxims_data *cximsd = cxlrd->platform_data;
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struct cxl_switch_decoder *cxlsd = &cxlrd->cxlsd;
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struct cxl_decoder *cxld = &cxlsd->cxld;
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int ig = cxld->interleave_granularity;
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int iw = cxld->interleave_ways;
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int n = 0;
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u64 hpa;
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if (dev_WARN_ONCE(&cxld->dev,
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cxld->interleave_ways != cxlsd->nr_targets,
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"misconfigured root decoder\n"))
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return NULL;
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hpa = cxlrd->res->start + pos * ig;
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/* Entry (n) is 0 for no interleave (iw == 1) */
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if (iw != 1)
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n = cxl_xor_calc_n(hpa, cximsd, iw, ig);
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if (n < 0)
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return NULL;
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return cxlrd->cxlsd.target[n];
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}
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struct cxl_cxims_context {
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struct device *dev;
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struct cxl_root_decoder *cxlrd;
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};
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static int cxl_parse_cxims(union acpi_subtable_headers *header, void *arg,
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const unsigned long end)
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{
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struct acpi_cedt_cxims *cxims = (struct acpi_cedt_cxims *)header;
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struct cxl_cxims_context *ctx = arg;
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struct cxl_root_decoder *cxlrd = ctx->cxlrd;
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struct cxl_decoder *cxld = &cxlrd->cxlsd.cxld;
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struct device *dev = ctx->dev;
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struct cxl_cxims_data *cximsd;
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unsigned int hbig, nr_maps;
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int rc;
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rc = eig_to_granularity(cxims->hbig, &hbig);
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if (rc)
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return rc;
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/* Does this CXIMS entry apply to the given CXL Window? */
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if (hbig != cxld->interleave_granularity)
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return 0;
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/* IW 1,3 do not use xormaps and skip this parsing entirely */
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if (is_power_of_2(cxld->interleave_ways))
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/* 2, 4, 8, 16 way */
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nr_maps = ilog2(cxld->interleave_ways);
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else
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/* 6, 12 way */
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nr_maps = ilog2(cxld->interleave_ways / 3);
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if (cxims->nr_xormaps < nr_maps) {
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dev_dbg(dev, "CXIMS nr_xormaps[%d] expected[%d]\n",
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cxims->nr_xormaps, nr_maps);
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return -ENXIO;
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}
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cximsd = devm_kzalloc(dev, struct_size(cximsd, xormaps, nr_maps),
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GFP_KERNEL);
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if (!cximsd)
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return -ENOMEM;
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cximsd->nr_maps = nr_maps;
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memcpy(cximsd->xormaps, cxims->xormap_list,
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nr_maps * sizeof(*cximsd->xormaps));
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cxlrd->platform_data = cximsd;
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return 0;
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}
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static unsigned long cfmws_to_decoder_flags(int restrictions)
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{
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unsigned long flags = CXL_DECODER_F_ENABLE;
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if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_TYPE2)
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flags |= CXL_DECODER_F_TYPE2;
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if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_TYPE3)
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flags |= CXL_DECODER_F_TYPE3;
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if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_VOLATILE)
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flags |= CXL_DECODER_F_RAM;
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if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_PMEM)
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flags |= CXL_DECODER_F_PMEM;
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if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_FIXED)
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flags |= CXL_DECODER_F_LOCK;
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return flags;
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}
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static int cxl_acpi_cfmws_verify(struct device *dev,
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struct acpi_cedt_cfmws *cfmws)
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{
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int rc, expected_len;
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unsigned int ways;
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if (cfmws->interleave_arithmetic != ACPI_CEDT_CFMWS_ARITHMETIC_MODULO &&
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cfmws->interleave_arithmetic != ACPI_CEDT_CFMWS_ARITHMETIC_XOR) {
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dev_err(dev, "CFMWS Unknown Interleave Arithmetic: %d\n",
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cfmws->interleave_arithmetic);
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return -EINVAL;
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}
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if (!IS_ALIGNED(cfmws->base_hpa, SZ_256M)) {
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dev_err(dev, "CFMWS Base HPA not 256MB aligned\n");
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return -EINVAL;
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}
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if (!IS_ALIGNED(cfmws->window_size, SZ_256M)) {
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dev_err(dev, "CFMWS Window Size not 256MB aligned\n");
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return -EINVAL;
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}
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rc = eiw_to_ways(cfmws->interleave_ways, &ways);
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if (rc) {
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dev_err(dev, "CFMWS Interleave Ways (%d) invalid\n",
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cfmws->interleave_ways);
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return -EINVAL;
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}
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expected_len = struct_size(cfmws, interleave_targets, ways);
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if (cfmws->header.length < expected_len) {
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dev_err(dev, "CFMWS length %d less than expected %d\n",
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cfmws->header.length, expected_len);
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return -EINVAL;
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}
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if (cfmws->header.length > expected_len)
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dev_dbg(dev, "CFMWS length %d greater than expected %d\n",
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cfmws->header.length, expected_len);
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return 0;
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}
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/*
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* Note, @dev must be the first member, see 'struct cxl_chbs_context'
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* and mock_acpi_table_parse_cedt()
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*/
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struct cxl_cfmws_context {
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struct device *dev;
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struct cxl_port *root_port;
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struct resource *cxl_res;
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int id;
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};
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static int cxl_parse_cfmws(union acpi_subtable_headers *header, void *arg,
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const unsigned long end)
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{
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int target_map[CXL_DECODER_MAX_INTERLEAVE];
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struct cxl_cfmws_context *ctx = arg;
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struct cxl_port *root_port = ctx->root_port;
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struct resource *cxl_res = ctx->cxl_res;
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struct cxl_cxims_context cxims_ctx;
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struct cxl_root_decoder *cxlrd;
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struct device *dev = ctx->dev;
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struct acpi_cedt_cfmws *cfmws;
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cxl_calc_hb_fn cxl_calc_hb;
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struct cxl_decoder *cxld;
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unsigned int ways, i, ig;
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struct resource *res;
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int rc;
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cfmws = (struct acpi_cedt_cfmws *) header;
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rc = cxl_acpi_cfmws_verify(dev, cfmws);
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if (rc) {
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dev_err(dev, "CFMWS range %#llx-%#llx not registered\n",
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cfmws->base_hpa,
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cfmws->base_hpa + cfmws->window_size - 1);
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return 0;
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}
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rc = eiw_to_ways(cfmws->interleave_ways, &ways);
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if (rc)
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return rc;
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rc = eig_to_granularity(cfmws->granularity, &ig);
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if (rc)
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return rc;
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for (i = 0; i < ways; i++)
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target_map[i] = cfmws->interleave_targets[i];
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res = kzalloc(sizeof(*res), GFP_KERNEL);
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if (!res)
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return -ENOMEM;
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res->name = kasprintf(GFP_KERNEL, "CXL Window %d", ctx->id++);
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if (!res->name)
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goto err_name;
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res->start = cfmws->base_hpa;
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res->end = cfmws->base_hpa + cfmws->window_size - 1;
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res->flags = IORESOURCE_MEM;
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/* add to the local resource tracking to establish a sort order */
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rc = insert_resource(cxl_res, res);
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if (rc)
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goto err_insert;
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if (cfmws->interleave_arithmetic == ACPI_CEDT_CFMWS_ARITHMETIC_MODULO)
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cxl_calc_hb = cxl_hb_modulo;
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else
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cxl_calc_hb = cxl_hb_xor;
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cxlrd = cxl_root_decoder_alloc(root_port, ways, cxl_calc_hb);
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if (IS_ERR(cxlrd))
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return 0;
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cxld = &cxlrd->cxlsd.cxld;
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cxld->flags = cfmws_to_decoder_flags(cfmws->restrictions);
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cxld->target_type = CXL_DECODER_HOSTONLYMEM;
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cxld->hpa_range = (struct range) {
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.start = res->start,
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.end = res->end,
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};
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cxld->interleave_ways = ways;
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/*
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* Minimize the x1 granularity to advertise support for any
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* valid region granularity
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*/
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if (ways == 1)
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ig = CXL_DECODER_MIN_GRANULARITY;
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cxld->interleave_granularity = ig;
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if (cfmws->interleave_arithmetic == ACPI_CEDT_CFMWS_ARITHMETIC_XOR) {
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if (ways != 1 && ways != 3) {
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cxims_ctx = (struct cxl_cxims_context) {
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.dev = dev,
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.cxlrd = cxlrd,
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};
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rc = acpi_table_parse_cedt(ACPI_CEDT_TYPE_CXIMS,
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cxl_parse_cxims, &cxims_ctx);
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if (rc < 0)
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goto err_xormap;
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if (!cxlrd->platform_data) {
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dev_err(dev, "No CXIMS for HBIG %u\n", ig);
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rc = -EINVAL;
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goto err_xormap;
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}
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}
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}
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rc = cxl_decoder_add(cxld, target_map);
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err_xormap:
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if (rc)
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put_device(&cxld->dev);
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else
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rc = cxl_decoder_autoremove(dev, cxld);
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if (rc) {
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dev_err(dev, "Failed to add decode range: %pr", res);
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return rc;
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}
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dev_dbg(dev, "add: %s node: %d range [%#llx - %#llx]\n",
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dev_name(&cxld->dev),
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phys_to_target_node(cxld->hpa_range.start),
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cxld->hpa_range.start, cxld->hpa_range.end);
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return 0;
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err_insert:
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kfree(res->name);
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err_name:
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kfree(res);
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return -ENOMEM;
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}
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__mock struct acpi_device *to_cxl_host_bridge(struct device *host,
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struct device *dev)
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{
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struct acpi_device *adev = to_acpi_device(dev);
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if (!acpi_pci_find_root(adev->handle))
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return NULL;
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if (strcmp(acpi_device_hid(adev), "ACPI0016") == 0)
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return adev;
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return NULL;
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}
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/* Note, @dev is used by mock_acpi_table_parse_cedt() */
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struct cxl_chbs_context {
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struct device *dev;
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unsigned long long uid;
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resource_size_t base;
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u32 cxl_version;
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};
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static int cxl_get_chbs_iter(union acpi_subtable_headers *header, void *arg,
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const unsigned long end)
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{
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struct cxl_chbs_context *ctx = arg;
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struct acpi_cedt_chbs *chbs;
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if (ctx->base != CXL_RESOURCE_NONE)
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return 0;
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chbs = (struct acpi_cedt_chbs *) header;
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if (ctx->uid != chbs->uid)
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return 0;
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ctx->cxl_version = chbs->cxl_version;
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if (!chbs->base)
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return 0;
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if (chbs->cxl_version == ACPI_CEDT_CHBS_VERSION_CXL11 &&
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chbs->length != CXL_RCRB_SIZE)
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return 0;
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ctx->base = chbs->base;
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return 0;
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}
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static int cxl_get_chbs(struct device *dev, struct acpi_device *hb,
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struct cxl_chbs_context *ctx)
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{
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unsigned long long uid;
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int rc;
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rc = acpi_evaluate_integer(hb->handle, METHOD_NAME__UID, NULL, &uid);
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if (rc != AE_OK) {
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dev_err(dev, "unable to retrieve _UID\n");
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return -ENOENT;
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}
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dev_dbg(dev, "UID found: %lld\n", uid);
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*ctx = (struct cxl_chbs_context) {
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.dev = dev,
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.uid = uid,
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.base = CXL_RESOURCE_NONE,
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.cxl_version = UINT_MAX,
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};
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acpi_table_parse_cedt(ACPI_CEDT_TYPE_CHBS, cxl_get_chbs_iter, ctx);
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return 0;
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}
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static int add_host_bridge_dport(struct device *match, void *arg)
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{
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acpi_status rc;
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struct device *bridge;
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struct cxl_dport *dport;
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struct cxl_chbs_context ctx;
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struct acpi_pci_root *pci_root;
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struct cxl_port *root_port = arg;
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struct device *host = root_port->dev.parent;
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struct acpi_device *hb = to_cxl_host_bridge(host, match);
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if (!hb)
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return 0;
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rc = cxl_get_chbs(match, hb, &ctx);
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if (rc)
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return rc;
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if (ctx.cxl_version == UINT_MAX) {
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dev_warn(match, "No CHBS found for Host Bridge (UID %lld)\n",
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ctx.uid);
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return 0;
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}
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if (ctx.base == CXL_RESOURCE_NONE) {
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dev_warn(match, "CHBS invalid for Host Bridge (UID %lld)\n",
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ctx.uid);
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return 0;
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}
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pci_root = acpi_pci_find_root(hb->handle);
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bridge = pci_root->bus->bridge;
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/*
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* In RCH mode, bind the component regs base to the dport. In
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* VH mode it will be bound to the CXL host bridge's port
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* object later in add_host_bridge_uport().
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*/
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if (ctx.cxl_version == ACPI_CEDT_CHBS_VERSION_CXL11) {
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dev_dbg(match, "RCRB found for UID %lld: %pa\n", ctx.uid,
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&ctx.base);
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dport = devm_cxl_add_rch_dport(root_port, bridge, ctx.uid,
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ctx.base);
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} else {
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dport = devm_cxl_add_dport(root_port, bridge, ctx.uid,
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CXL_RESOURCE_NONE);
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}
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if (IS_ERR(dport))
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return PTR_ERR(dport);
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return 0;
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}
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|
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/*
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* A host bridge is a dport to a CFMWS decode and it is a uport to the
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* dport (PCIe Root Ports) in the host bridge.
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*/
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static int add_host_bridge_uport(struct device *match, void *arg)
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{
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struct cxl_port *root_port = arg;
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struct device *host = root_port->dev.parent;
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struct acpi_device *hb = to_cxl_host_bridge(host, match);
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struct acpi_pci_root *pci_root;
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struct cxl_dport *dport;
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struct cxl_port *port;
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struct device *bridge;
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struct cxl_chbs_context ctx;
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resource_size_t component_reg_phys;
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int rc;
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|
if (!hb)
|
|
return 0;
|
|
|
|
pci_root = acpi_pci_find_root(hb->handle);
|
|
bridge = pci_root->bus->bridge;
|
|
dport = cxl_find_dport_by_dev(root_port, bridge);
|
|
if (!dport) {
|
|
dev_dbg(host, "host bridge expected and not found\n");
|
|
return 0;
|
|
}
|
|
|
|
if (dport->rch) {
|
|
dev_info(bridge, "host supports CXL (restricted)\n");
|
|
return 0;
|
|
}
|
|
|
|
rc = cxl_get_chbs(match, hb, &ctx);
|
|
if (rc)
|
|
return rc;
|
|
|
|
if (ctx.cxl_version == ACPI_CEDT_CHBS_VERSION_CXL11) {
|
|
dev_warn(bridge,
|
|
"CXL CHBS version mismatch, skip port registration\n");
|
|
return 0;
|
|
}
|
|
|
|
component_reg_phys = ctx.base;
|
|
if (component_reg_phys != CXL_RESOURCE_NONE)
|
|
dev_dbg(match, "CHBCR found for UID %lld: %pa\n",
|
|
ctx.uid, &component_reg_phys);
|
|
|
|
rc = devm_cxl_register_pci_bus(host, bridge, pci_root->bus);
|
|
if (rc)
|
|
return rc;
|
|
|
|
port = devm_cxl_add_port(host, bridge, component_reg_phys, dport);
|
|
if (IS_ERR(port))
|
|
return PTR_ERR(port);
|
|
|
|
dev_info(bridge, "host supports CXL\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int add_root_nvdimm_bridge(struct device *match, void *data)
|
|
{
|
|
struct cxl_decoder *cxld;
|
|
struct cxl_port *root_port = data;
|
|
struct cxl_nvdimm_bridge *cxl_nvb;
|
|
struct device *host = root_port->dev.parent;
|
|
|
|
if (!is_root_decoder(match))
|
|
return 0;
|
|
|
|
cxld = to_cxl_decoder(match);
|
|
if (!(cxld->flags & CXL_DECODER_F_PMEM))
|
|
return 0;
|
|
|
|
cxl_nvb = devm_cxl_add_nvdimm_bridge(host, root_port);
|
|
if (IS_ERR(cxl_nvb)) {
|
|
dev_dbg(host, "failed to register pmem\n");
|
|
return PTR_ERR(cxl_nvb);
|
|
}
|
|
dev_dbg(host, "%s: add: %s\n", dev_name(&root_port->dev),
|
|
dev_name(&cxl_nvb->dev));
|
|
return 1;
|
|
}
|
|
|
|
static struct lock_class_key cxl_root_key;
|
|
|
|
static void cxl_acpi_lock_reset_class(void *dev)
|
|
{
|
|
device_lock_reset_class(dev);
|
|
}
|
|
|
|
static void del_cxl_resource(struct resource *res)
|
|
{
|
|
kfree(res->name);
|
|
kfree(res);
|
|
}
|
|
|
|
static void cxl_set_public_resource(struct resource *priv, struct resource *pub)
|
|
{
|
|
priv->desc = (unsigned long) pub;
|
|
}
|
|
|
|
static struct resource *cxl_get_public_resource(struct resource *priv)
|
|
{
|
|
return (struct resource *) priv->desc;
|
|
}
|
|
|
|
static void remove_cxl_resources(void *data)
|
|
{
|
|
struct resource *res, *next, *cxl = data;
|
|
|
|
for (res = cxl->child; res; res = next) {
|
|
struct resource *victim = cxl_get_public_resource(res);
|
|
|
|
next = res->sibling;
|
|
remove_resource(res);
|
|
|
|
if (victim) {
|
|
remove_resource(victim);
|
|
kfree(victim);
|
|
}
|
|
|
|
del_cxl_resource(res);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* add_cxl_resources() - reflect CXL fixed memory windows in iomem_resource
|
|
* @cxl_res: A standalone resource tree where each CXL window is a sibling
|
|
*
|
|
* Walk each CXL window in @cxl_res and add it to iomem_resource potentially
|
|
* expanding its boundaries to ensure that any conflicting resources become
|
|
* children. If a window is expanded it may then conflict with a another window
|
|
* entry and require the window to be truncated or trimmed. Consider this
|
|
* situation:
|
|
*
|
|
* |-- "CXL Window 0" --||----- "CXL Window 1" -----|
|
|
* |--------------- "System RAM" -------------|
|
|
*
|
|
* ...where platform firmware has established as System RAM resource across 2
|
|
* windows, but has left some portion of window 1 for dynamic CXL region
|
|
* provisioning. In this case "Window 0" will span the entirety of the "System
|
|
* RAM" span, and "CXL Window 1" is truncated to the remaining tail past the end
|
|
* of that "System RAM" resource.
|
|
*/
|
|
static int add_cxl_resources(struct resource *cxl_res)
|
|
{
|
|
struct resource *res, *new, *next;
|
|
|
|
for (res = cxl_res->child; res; res = next) {
|
|
new = kzalloc(sizeof(*new), GFP_KERNEL);
|
|
if (!new)
|
|
return -ENOMEM;
|
|
new->name = res->name;
|
|
new->start = res->start;
|
|
new->end = res->end;
|
|
new->flags = IORESOURCE_MEM;
|
|
new->desc = IORES_DESC_CXL;
|
|
|
|
/*
|
|
* Record the public resource in the private cxl_res tree for
|
|
* later removal.
|
|
*/
|
|
cxl_set_public_resource(res, new);
|
|
|
|
insert_resource_expand_to_fit(&iomem_resource, new);
|
|
|
|
next = res->sibling;
|
|
while (next && resource_overlaps(new, next)) {
|
|
if (resource_contains(new, next)) {
|
|
struct resource *_next = next->sibling;
|
|
|
|
remove_resource(next);
|
|
del_cxl_resource(next);
|
|
next = _next;
|
|
} else
|
|
next->start = new->end + 1;
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int pair_cxl_resource(struct device *dev, void *data)
|
|
{
|
|
struct resource *cxl_res = data;
|
|
struct resource *p;
|
|
|
|
if (!is_root_decoder(dev))
|
|
return 0;
|
|
|
|
for (p = cxl_res->child; p; p = p->sibling) {
|
|
struct cxl_root_decoder *cxlrd = to_cxl_root_decoder(dev);
|
|
struct cxl_decoder *cxld = &cxlrd->cxlsd.cxld;
|
|
struct resource res = {
|
|
.start = cxld->hpa_range.start,
|
|
.end = cxld->hpa_range.end,
|
|
.flags = IORESOURCE_MEM,
|
|
};
|
|
|
|
if (resource_contains(p, &res)) {
|
|
cxlrd->res = cxl_get_public_resource(p);
|
|
break;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cxl_acpi_probe(struct platform_device *pdev)
|
|
{
|
|
int rc;
|
|
struct resource *cxl_res;
|
|
struct cxl_port *root_port;
|
|
struct device *host = &pdev->dev;
|
|
struct acpi_device *adev = ACPI_COMPANION(host);
|
|
struct cxl_cfmws_context ctx;
|
|
|
|
device_lock_set_class(&pdev->dev, &cxl_root_key);
|
|
rc = devm_add_action_or_reset(&pdev->dev, cxl_acpi_lock_reset_class,
|
|
&pdev->dev);
|
|
if (rc)
|
|
return rc;
|
|
|
|
cxl_res = devm_kzalloc(host, sizeof(*cxl_res), GFP_KERNEL);
|
|
if (!cxl_res)
|
|
return -ENOMEM;
|
|
cxl_res->name = "CXL mem";
|
|
cxl_res->start = 0;
|
|
cxl_res->end = -1;
|
|
cxl_res->flags = IORESOURCE_MEM;
|
|
|
|
root_port = devm_cxl_add_port(host, host, CXL_RESOURCE_NONE, NULL);
|
|
if (IS_ERR(root_port))
|
|
return PTR_ERR(root_port);
|
|
|
|
rc = bus_for_each_dev(adev->dev.bus, NULL, root_port,
|
|
add_host_bridge_dport);
|
|
if (rc < 0)
|
|
return rc;
|
|
|
|
rc = devm_add_action_or_reset(host, remove_cxl_resources, cxl_res);
|
|
if (rc)
|
|
return rc;
|
|
|
|
ctx = (struct cxl_cfmws_context) {
|
|
.dev = host,
|
|
.root_port = root_port,
|
|
.cxl_res = cxl_res,
|
|
};
|
|
rc = acpi_table_parse_cedt(ACPI_CEDT_TYPE_CFMWS, cxl_parse_cfmws, &ctx);
|
|
if (rc < 0)
|
|
return -ENXIO;
|
|
|
|
rc = add_cxl_resources(cxl_res);
|
|
if (rc)
|
|
return rc;
|
|
|
|
/*
|
|
* Populate the root decoders with their related iomem resource,
|
|
* if present
|
|
*/
|
|
device_for_each_child(&root_port->dev, cxl_res, pair_cxl_resource);
|
|
|
|
/*
|
|
* Root level scanned with host-bridge as dports, now scan host-bridges
|
|
* for their role as CXL uports to their CXL-capable PCIe Root Ports.
|
|
*/
|
|
rc = bus_for_each_dev(adev->dev.bus, NULL, root_port,
|
|
add_host_bridge_uport);
|
|
if (rc < 0)
|
|
return rc;
|
|
|
|
if (IS_ENABLED(CONFIG_CXL_PMEM))
|
|
rc = device_for_each_child(&root_port->dev, root_port,
|
|
add_root_nvdimm_bridge);
|
|
if (rc < 0)
|
|
return rc;
|
|
|
|
/* In case PCI is scanned before ACPI re-trigger memdev attach */
|
|
cxl_bus_rescan();
|
|
return 0;
|
|
}
|
|
|
|
static const struct acpi_device_id cxl_acpi_ids[] = {
|
|
{ "ACPI0017" },
|
|
{ },
|
|
};
|
|
MODULE_DEVICE_TABLE(acpi, cxl_acpi_ids);
|
|
|
|
static const struct platform_device_id cxl_test_ids[] = {
|
|
{ "cxl_acpi" },
|
|
{ },
|
|
};
|
|
MODULE_DEVICE_TABLE(platform, cxl_test_ids);
|
|
|
|
static struct platform_driver cxl_acpi_driver = {
|
|
.probe = cxl_acpi_probe,
|
|
.driver = {
|
|
.name = KBUILD_MODNAME,
|
|
.acpi_match_table = cxl_acpi_ids,
|
|
},
|
|
.id_table = cxl_test_ids,
|
|
};
|
|
|
|
static int __init cxl_acpi_init(void)
|
|
{
|
|
return platform_driver_register(&cxl_acpi_driver);
|
|
}
|
|
|
|
static void __exit cxl_acpi_exit(void)
|
|
{
|
|
platform_driver_unregister(&cxl_acpi_driver);
|
|
cxl_bus_drain();
|
|
}
|
|
|
|
/* load before dax_hmem sees 'Soft Reserved' CXL ranges */
|
|
subsys_initcall(cxl_acpi_init);
|
|
module_exit(cxl_acpi_exit);
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_IMPORT_NS(CXL);
|
|
MODULE_IMPORT_NS(ACPI);
|