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![Andy Shevchenko](/assets/img/avatar_default.png)
The pdev member is assigned and not used, drop it. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
656 lines
17 KiB
C
656 lines
17 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Broadcom Kona GPIO Driver
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*
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* Author: Broadcom Corporation <bcm-kernel-feedback-list@broadcom.com>
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* Copyright (C) 2012-2014 Broadcom Corporation
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*/
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#include <linux/bitops.h>
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#include <linux/err.h>
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#include <linux/gpio/driver.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/irqdomain.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/mod_devicetable.h>
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#include <linux/platform_device.h>
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#include <linux/property.h>
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#define BCM_GPIO_PASSWD 0x00a5a501
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#define GPIO_PER_BANK 32
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#define GPIO_MAX_BANK_NUM 8
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#define GPIO_BANK(gpio) ((gpio) >> 5)
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#define GPIO_BIT(gpio) ((gpio) & (GPIO_PER_BANK - 1))
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/* There is a GPIO control register for each GPIO */
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#define GPIO_CONTROL(gpio) (0x00000100 + ((gpio) << 2))
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/* The remaining registers are per GPIO bank */
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#define GPIO_OUT_STATUS(bank) (0x00000000 + ((bank) << 2))
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#define GPIO_IN_STATUS(bank) (0x00000020 + ((bank) << 2))
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#define GPIO_OUT_SET(bank) (0x00000040 + ((bank) << 2))
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#define GPIO_OUT_CLEAR(bank) (0x00000060 + ((bank) << 2))
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#define GPIO_INT_STATUS(bank) (0x00000080 + ((bank) << 2))
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#define GPIO_INT_MASK(bank) (0x000000a0 + ((bank) << 2))
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#define GPIO_INT_MSKCLR(bank) (0x000000c0 + ((bank) << 2))
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#define GPIO_PWD_STATUS(bank) (0x00000500 + ((bank) << 2))
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#define GPIO_GPPWR_OFFSET 0x00000520
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#define GPIO_GPCTR0_DBR_SHIFT 5
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#define GPIO_GPCTR0_DBR_MASK 0x000001e0
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#define GPIO_GPCTR0_ITR_SHIFT 3
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#define GPIO_GPCTR0_ITR_MASK 0x00000018
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#define GPIO_GPCTR0_ITR_CMD_RISING_EDGE 0x00000001
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#define GPIO_GPCTR0_ITR_CMD_FALLING_EDGE 0x00000002
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#define GPIO_GPCTR0_ITR_CMD_BOTH_EDGE 0x00000003
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#define GPIO_GPCTR0_IOTR_MASK 0x00000001
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#define GPIO_GPCTR0_IOTR_CMD_0UTPUT 0x00000000
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#define GPIO_GPCTR0_IOTR_CMD_INPUT 0x00000001
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#define GPIO_GPCTR0_DB_ENABLE_MASK 0x00000100
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#define LOCK_CODE 0xffffffff
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#define UNLOCK_CODE 0x00000000
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struct bcm_kona_gpio {
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void __iomem *reg_base;
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int num_bank;
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raw_spinlock_t lock;
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struct gpio_chip gpio_chip;
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struct irq_domain *irq_domain;
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struct bcm_kona_gpio_bank *banks;
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};
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struct bcm_kona_gpio_bank {
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int id;
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int irq;
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/* Used in the interrupt handler */
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struct bcm_kona_gpio *kona_gpio;
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};
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static inline void bcm_kona_gpio_write_lock_regs(void __iomem *reg_base,
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int bank_id, u32 lockcode)
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{
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writel(BCM_GPIO_PASSWD, reg_base + GPIO_GPPWR_OFFSET);
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writel(lockcode, reg_base + GPIO_PWD_STATUS(bank_id));
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}
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static void bcm_kona_gpio_lock_gpio(struct bcm_kona_gpio *kona_gpio,
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unsigned gpio)
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{
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u32 val;
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unsigned long flags;
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int bank_id = GPIO_BANK(gpio);
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raw_spin_lock_irqsave(&kona_gpio->lock, flags);
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val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));
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val |= BIT(gpio);
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bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);
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raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
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}
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static void bcm_kona_gpio_unlock_gpio(struct bcm_kona_gpio *kona_gpio,
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unsigned gpio)
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{
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u32 val;
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unsigned long flags;
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int bank_id = GPIO_BANK(gpio);
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raw_spin_lock_irqsave(&kona_gpio->lock, flags);
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val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));
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val &= ~BIT(gpio);
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bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);
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raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
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}
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static int bcm_kona_gpio_get_dir(struct gpio_chip *chip, unsigned gpio)
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{
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struct bcm_kona_gpio *kona_gpio = gpiochip_get_data(chip);
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void __iomem *reg_base = kona_gpio->reg_base;
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u32 val;
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val = readl(reg_base + GPIO_CONTROL(gpio)) & GPIO_GPCTR0_IOTR_MASK;
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return val ? GPIO_LINE_DIRECTION_IN : GPIO_LINE_DIRECTION_OUT;
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}
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static void bcm_kona_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
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{
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struct bcm_kona_gpio *kona_gpio;
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void __iomem *reg_base;
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int bank_id = GPIO_BANK(gpio);
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int bit = GPIO_BIT(gpio);
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u32 val, reg_offset;
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unsigned long flags;
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kona_gpio = gpiochip_get_data(chip);
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reg_base = kona_gpio->reg_base;
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raw_spin_lock_irqsave(&kona_gpio->lock, flags);
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/* this function only applies to output pin */
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if (bcm_kona_gpio_get_dir(chip, gpio) == GPIO_LINE_DIRECTION_IN)
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goto out;
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reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);
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val = readl(reg_base + reg_offset);
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val |= BIT(bit);
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writel(val, reg_base + reg_offset);
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out:
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raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
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}
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static int bcm_kona_gpio_get(struct gpio_chip *chip, unsigned gpio)
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{
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struct bcm_kona_gpio *kona_gpio;
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void __iomem *reg_base;
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int bank_id = GPIO_BANK(gpio);
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int bit = GPIO_BIT(gpio);
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u32 val, reg_offset;
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unsigned long flags;
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kona_gpio = gpiochip_get_data(chip);
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reg_base = kona_gpio->reg_base;
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raw_spin_lock_irqsave(&kona_gpio->lock, flags);
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if (bcm_kona_gpio_get_dir(chip, gpio) == GPIO_LINE_DIRECTION_IN)
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reg_offset = GPIO_IN_STATUS(bank_id);
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else
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reg_offset = GPIO_OUT_STATUS(bank_id);
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/* read the GPIO bank status */
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val = readl(reg_base + reg_offset);
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raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
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/* return the specified bit status */
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return !!(val & BIT(bit));
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}
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static int bcm_kona_gpio_request(struct gpio_chip *chip, unsigned gpio)
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{
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struct bcm_kona_gpio *kona_gpio = gpiochip_get_data(chip);
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bcm_kona_gpio_unlock_gpio(kona_gpio, gpio);
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return 0;
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}
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static void bcm_kona_gpio_free(struct gpio_chip *chip, unsigned gpio)
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{
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struct bcm_kona_gpio *kona_gpio = gpiochip_get_data(chip);
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bcm_kona_gpio_lock_gpio(kona_gpio, gpio);
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}
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static int bcm_kona_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
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{
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struct bcm_kona_gpio *kona_gpio;
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void __iomem *reg_base;
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u32 val;
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unsigned long flags;
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kona_gpio = gpiochip_get_data(chip);
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reg_base = kona_gpio->reg_base;
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raw_spin_lock_irqsave(&kona_gpio->lock, flags);
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val = readl(reg_base + GPIO_CONTROL(gpio));
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val &= ~GPIO_GPCTR0_IOTR_MASK;
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val |= GPIO_GPCTR0_IOTR_CMD_INPUT;
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writel(val, reg_base + GPIO_CONTROL(gpio));
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raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
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return 0;
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}
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static int bcm_kona_gpio_direction_output(struct gpio_chip *chip,
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unsigned gpio, int value)
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{
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struct bcm_kona_gpio *kona_gpio;
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void __iomem *reg_base;
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int bank_id = GPIO_BANK(gpio);
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int bit = GPIO_BIT(gpio);
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u32 val, reg_offset;
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unsigned long flags;
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kona_gpio = gpiochip_get_data(chip);
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reg_base = kona_gpio->reg_base;
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raw_spin_lock_irqsave(&kona_gpio->lock, flags);
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val = readl(reg_base + GPIO_CONTROL(gpio));
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val &= ~GPIO_GPCTR0_IOTR_MASK;
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val |= GPIO_GPCTR0_IOTR_CMD_0UTPUT;
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writel(val, reg_base + GPIO_CONTROL(gpio));
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reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);
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val = readl(reg_base + reg_offset);
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val |= BIT(bit);
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writel(val, reg_base + reg_offset);
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raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
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return 0;
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}
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static int bcm_kona_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
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{
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struct bcm_kona_gpio *kona_gpio;
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kona_gpio = gpiochip_get_data(chip);
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if (gpio >= kona_gpio->gpio_chip.ngpio)
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return -ENXIO;
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return irq_create_mapping(kona_gpio->irq_domain, gpio);
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}
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static int bcm_kona_gpio_set_debounce(struct gpio_chip *chip, unsigned gpio,
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unsigned debounce)
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{
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struct bcm_kona_gpio *kona_gpio;
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void __iomem *reg_base;
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u32 val, res;
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unsigned long flags;
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kona_gpio = gpiochip_get_data(chip);
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reg_base = kona_gpio->reg_base;
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/* debounce must be 1-128ms (or 0) */
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if ((debounce > 0 && debounce < 1000) || debounce > 128000) {
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dev_err(chip->parent, "Debounce value %u not in range\n",
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debounce);
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return -EINVAL;
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}
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/* calculate debounce bit value */
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if (debounce != 0) {
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/* Convert to ms */
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debounce /= 1000;
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/* find the MSB */
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res = fls(debounce) - 1;
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/* Check if MSB-1 is set (round up or down) */
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if (res > 0 && (debounce & BIT(res - 1)))
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res++;
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}
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/* spin lock for read-modify-write of the GPIO register */
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raw_spin_lock_irqsave(&kona_gpio->lock, flags);
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val = readl(reg_base + GPIO_CONTROL(gpio));
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val &= ~GPIO_GPCTR0_DBR_MASK;
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if (debounce == 0) {
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/* disable debounce */
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val &= ~GPIO_GPCTR0_DB_ENABLE_MASK;
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} else {
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val |= GPIO_GPCTR0_DB_ENABLE_MASK |
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(res << GPIO_GPCTR0_DBR_SHIFT);
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}
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writel(val, reg_base + GPIO_CONTROL(gpio));
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raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
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return 0;
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}
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static int bcm_kona_gpio_set_config(struct gpio_chip *chip, unsigned gpio,
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unsigned long config)
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{
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u32 debounce;
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if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
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return -ENOTSUPP;
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debounce = pinconf_to_config_argument(config);
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return bcm_kona_gpio_set_debounce(chip, gpio, debounce);
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}
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static const struct gpio_chip template_chip = {
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.label = "bcm-kona-gpio",
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.owner = THIS_MODULE,
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.request = bcm_kona_gpio_request,
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.free = bcm_kona_gpio_free,
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.get_direction = bcm_kona_gpio_get_dir,
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.direction_input = bcm_kona_gpio_direction_input,
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.get = bcm_kona_gpio_get,
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.direction_output = bcm_kona_gpio_direction_output,
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.set = bcm_kona_gpio_set,
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.set_config = bcm_kona_gpio_set_config,
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.to_irq = bcm_kona_gpio_to_irq,
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.base = 0,
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};
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static void bcm_kona_gpio_irq_ack(struct irq_data *d)
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{
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struct bcm_kona_gpio *kona_gpio;
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void __iomem *reg_base;
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unsigned gpio = d->hwirq;
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int bank_id = GPIO_BANK(gpio);
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int bit = GPIO_BIT(gpio);
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u32 val;
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unsigned long flags;
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kona_gpio = irq_data_get_irq_chip_data(d);
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reg_base = kona_gpio->reg_base;
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raw_spin_lock_irqsave(&kona_gpio->lock, flags);
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val = readl(reg_base + GPIO_INT_STATUS(bank_id));
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val |= BIT(bit);
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writel(val, reg_base + GPIO_INT_STATUS(bank_id));
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raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
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}
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static void bcm_kona_gpio_irq_mask(struct irq_data *d)
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{
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struct bcm_kona_gpio *kona_gpio;
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void __iomem *reg_base;
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unsigned gpio = d->hwirq;
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int bank_id = GPIO_BANK(gpio);
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int bit = GPIO_BIT(gpio);
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u32 val;
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unsigned long flags;
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kona_gpio = irq_data_get_irq_chip_data(d);
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reg_base = kona_gpio->reg_base;
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raw_spin_lock_irqsave(&kona_gpio->lock, flags);
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val = readl(reg_base + GPIO_INT_MASK(bank_id));
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val |= BIT(bit);
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writel(val, reg_base + GPIO_INT_MASK(bank_id));
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gpiochip_disable_irq(&kona_gpio->gpio_chip, gpio);
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raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
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}
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static void bcm_kona_gpio_irq_unmask(struct irq_data *d)
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{
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struct bcm_kona_gpio *kona_gpio;
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void __iomem *reg_base;
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unsigned gpio = d->hwirq;
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int bank_id = GPIO_BANK(gpio);
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int bit = GPIO_BIT(gpio);
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u32 val;
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unsigned long flags;
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kona_gpio = irq_data_get_irq_chip_data(d);
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reg_base = kona_gpio->reg_base;
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raw_spin_lock_irqsave(&kona_gpio->lock, flags);
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val = readl(reg_base + GPIO_INT_MSKCLR(bank_id));
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val |= BIT(bit);
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writel(val, reg_base + GPIO_INT_MSKCLR(bank_id));
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gpiochip_enable_irq(&kona_gpio->gpio_chip, gpio);
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raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
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}
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static int bcm_kona_gpio_irq_set_type(struct irq_data *d, unsigned int type)
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{
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struct bcm_kona_gpio *kona_gpio;
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void __iomem *reg_base;
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unsigned gpio = d->hwirq;
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u32 lvl_type;
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u32 val;
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unsigned long flags;
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kona_gpio = irq_data_get_irq_chip_data(d);
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reg_base = kona_gpio->reg_base;
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switch (type & IRQ_TYPE_SENSE_MASK) {
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case IRQ_TYPE_EDGE_RISING:
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lvl_type = GPIO_GPCTR0_ITR_CMD_RISING_EDGE;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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lvl_type = GPIO_GPCTR0_ITR_CMD_FALLING_EDGE;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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lvl_type = GPIO_GPCTR0_ITR_CMD_BOTH_EDGE;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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case IRQ_TYPE_LEVEL_LOW:
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/* BCM GPIO doesn't support level triggering */
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default:
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dev_err(kona_gpio->gpio_chip.parent,
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"Invalid BCM GPIO irq type 0x%x\n", type);
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return -EINVAL;
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}
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raw_spin_lock_irqsave(&kona_gpio->lock, flags);
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val = readl(reg_base + GPIO_CONTROL(gpio));
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val &= ~GPIO_GPCTR0_ITR_MASK;
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val |= lvl_type << GPIO_GPCTR0_ITR_SHIFT;
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writel(val, reg_base + GPIO_CONTROL(gpio));
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raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
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return 0;
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}
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static void bcm_kona_gpio_irq_handler(struct irq_desc *desc)
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{
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void __iomem *reg_base;
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int bit, bank_id;
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unsigned long sta;
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struct bcm_kona_gpio_bank *bank = irq_desc_get_handler_data(desc);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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chained_irq_enter(chip, desc);
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/*
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* For bank interrupts, we can't use chip_data to store the kona_gpio
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* pointer, since GIC needs it for its own purposes. Therefore, we get
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* our pointer from the bank structure.
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*/
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reg_base = bank->kona_gpio->reg_base;
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bank_id = bank->id;
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while ((sta = readl(reg_base + GPIO_INT_STATUS(bank_id)) &
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(~(readl(reg_base + GPIO_INT_MASK(bank_id)))))) {
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for_each_set_bit(bit, &sta, 32) {
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int hwirq = GPIO_PER_BANK * bank_id + bit;
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/*
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* Clear interrupt before handler is called so we don't
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* miss any interrupt occurred during executing them.
|
|
*/
|
|
writel(readl(reg_base + GPIO_INT_STATUS(bank_id)) |
|
|
BIT(bit), reg_base + GPIO_INT_STATUS(bank_id));
|
|
/* Invoke interrupt handler */
|
|
generic_handle_domain_irq(bank->kona_gpio->irq_domain,
|
|
hwirq);
|
|
}
|
|
}
|
|
|
|
chained_irq_exit(chip, desc);
|
|
}
|
|
|
|
static int bcm_kona_gpio_irq_reqres(struct irq_data *d)
|
|
{
|
|
struct bcm_kona_gpio *kona_gpio = irq_data_get_irq_chip_data(d);
|
|
|
|
return gpiochip_reqres_irq(&kona_gpio->gpio_chip, d->hwirq);
|
|
}
|
|
|
|
static void bcm_kona_gpio_irq_relres(struct irq_data *d)
|
|
{
|
|
struct bcm_kona_gpio *kona_gpio = irq_data_get_irq_chip_data(d);
|
|
|
|
gpiochip_relres_irq(&kona_gpio->gpio_chip, d->hwirq);
|
|
}
|
|
|
|
static struct irq_chip bcm_gpio_irq_chip = {
|
|
.name = "bcm-kona-gpio",
|
|
.irq_ack = bcm_kona_gpio_irq_ack,
|
|
.irq_mask = bcm_kona_gpio_irq_mask,
|
|
.irq_unmask = bcm_kona_gpio_irq_unmask,
|
|
.irq_set_type = bcm_kona_gpio_irq_set_type,
|
|
.irq_request_resources = bcm_kona_gpio_irq_reqres,
|
|
.irq_release_resources = bcm_kona_gpio_irq_relres,
|
|
};
|
|
|
|
static struct of_device_id const bcm_kona_gpio_of_match[] = {
|
|
{ .compatible = "brcm,kona-gpio" },
|
|
{}
|
|
};
|
|
|
|
/*
|
|
* This lock class tells lockdep that GPIO irqs are in a different
|
|
* category than their parents, so it won't report false recursion.
|
|
*/
|
|
static struct lock_class_key gpio_lock_class;
|
|
static struct lock_class_key gpio_request_class;
|
|
|
|
static int bcm_kona_gpio_irq_map(struct irq_domain *d, unsigned int irq,
|
|
irq_hw_number_t hwirq)
|
|
{
|
|
int ret;
|
|
|
|
ret = irq_set_chip_data(irq, d->host_data);
|
|
if (ret < 0)
|
|
return ret;
|
|
irq_set_lockdep_class(irq, &gpio_lock_class, &gpio_request_class);
|
|
irq_set_chip_and_handler(irq, &bcm_gpio_irq_chip, handle_simple_irq);
|
|
irq_set_noprobe(irq);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void bcm_kona_gpio_irq_unmap(struct irq_domain *d, unsigned int irq)
|
|
{
|
|
irq_set_chip_and_handler(irq, NULL, NULL);
|
|
irq_set_chip_data(irq, NULL);
|
|
}
|
|
|
|
static const struct irq_domain_ops bcm_kona_irq_ops = {
|
|
.map = bcm_kona_gpio_irq_map,
|
|
.unmap = bcm_kona_gpio_irq_unmap,
|
|
.xlate = irq_domain_xlate_twocell,
|
|
};
|
|
|
|
static void bcm_kona_gpio_reset(struct bcm_kona_gpio *kona_gpio)
|
|
{
|
|
void __iomem *reg_base;
|
|
int i;
|
|
|
|
reg_base = kona_gpio->reg_base;
|
|
/* disable interrupts and clear status */
|
|
for (i = 0; i < kona_gpio->num_bank; i++) {
|
|
/* Unlock the entire bank first */
|
|
bcm_kona_gpio_write_lock_regs(reg_base, i, UNLOCK_CODE);
|
|
writel(0xffffffff, reg_base + GPIO_INT_MASK(i));
|
|
writel(0xffffffff, reg_base + GPIO_INT_STATUS(i));
|
|
/* Now re-lock the bank */
|
|
bcm_kona_gpio_write_lock_regs(reg_base, i, LOCK_CODE);
|
|
}
|
|
}
|
|
|
|
static int bcm_kona_gpio_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct bcm_kona_gpio_bank *bank;
|
|
struct bcm_kona_gpio *kona_gpio;
|
|
struct gpio_chip *chip;
|
|
int ret;
|
|
int i;
|
|
|
|
kona_gpio = devm_kzalloc(dev, sizeof(*kona_gpio), GFP_KERNEL);
|
|
if (!kona_gpio)
|
|
return -ENOMEM;
|
|
|
|
kona_gpio->gpio_chip = template_chip;
|
|
chip = &kona_gpio->gpio_chip;
|
|
ret = platform_irq_count(pdev);
|
|
if (!ret) {
|
|
dev_err(dev, "Couldn't determine # GPIO banks\n");
|
|
return -ENOENT;
|
|
} else if (ret < 0) {
|
|
return dev_err_probe(dev, ret, "Couldn't determine GPIO banks\n");
|
|
}
|
|
kona_gpio->num_bank = ret;
|
|
|
|
if (kona_gpio->num_bank > GPIO_MAX_BANK_NUM) {
|
|
dev_err(dev, "Too many GPIO banks configured (max=%d)\n",
|
|
GPIO_MAX_BANK_NUM);
|
|
return -ENXIO;
|
|
}
|
|
kona_gpio->banks = devm_kcalloc(dev,
|
|
kona_gpio->num_bank,
|
|
sizeof(*kona_gpio->banks),
|
|
GFP_KERNEL);
|
|
if (!kona_gpio->banks)
|
|
return -ENOMEM;
|
|
|
|
chip->parent = dev;
|
|
chip->ngpio = kona_gpio->num_bank * GPIO_PER_BANK;
|
|
|
|
kona_gpio->irq_domain = irq_domain_create_linear(dev_fwnode(dev),
|
|
chip->ngpio,
|
|
&bcm_kona_irq_ops,
|
|
kona_gpio);
|
|
if (!kona_gpio->irq_domain) {
|
|
dev_err(dev, "Couldn't allocate IRQ domain\n");
|
|
return -ENXIO;
|
|
}
|
|
|
|
kona_gpio->reg_base = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(kona_gpio->reg_base)) {
|
|
ret = PTR_ERR(kona_gpio->reg_base);
|
|
goto err_irq_domain;
|
|
}
|
|
|
|
for (i = 0; i < kona_gpio->num_bank; i++) {
|
|
bank = &kona_gpio->banks[i];
|
|
bank->id = i;
|
|
bank->irq = platform_get_irq(pdev, i);
|
|
bank->kona_gpio = kona_gpio;
|
|
if (bank->irq < 0) {
|
|
dev_err(dev, "Couldn't get IRQ for bank %d", i);
|
|
ret = -ENOENT;
|
|
goto err_irq_domain;
|
|
}
|
|
}
|
|
|
|
dev_info(&pdev->dev, "Setting up Kona GPIO\n");
|
|
|
|
bcm_kona_gpio_reset(kona_gpio);
|
|
|
|
ret = devm_gpiochip_add_data(dev, chip, kona_gpio);
|
|
if (ret < 0) {
|
|
dev_err(dev, "Couldn't add GPIO chip -- %d\n", ret);
|
|
goto err_irq_domain;
|
|
}
|
|
for (i = 0; i < kona_gpio->num_bank; i++) {
|
|
bank = &kona_gpio->banks[i];
|
|
irq_set_chained_handler_and_data(bank->irq,
|
|
bcm_kona_gpio_irq_handler,
|
|
bank);
|
|
}
|
|
|
|
raw_spin_lock_init(&kona_gpio->lock);
|
|
|
|
return 0;
|
|
|
|
err_irq_domain:
|
|
irq_domain_remove(kona_gpio->irq_domain);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static struct platform_driver bcm_kona_gpio_driver = {
|
|
.driver = {
|
|
.name = "bcm-kona-gpio",
|
|
.of_match_table = bcm_kona_gpio_of_match,
|
|
},
|
|
.probe = bcm_kona_gpio_probe,
|
|
};
|
|
builtin_platform_driver(bcm_kona_gpio_driver);
|