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![Rob Herring](/assets/img/avatar_default.png)
The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Acked-by: Romain Perier <romain.perier@gmail.com> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
319 lines
9 KiB
C
319 lines
9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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// Copyright (C) 2008-2009 The GameCube Linux Team
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// Copyright (C) 2008,2009 Albert Herranz
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// Copyright (C) 2017-2018 Jonathan Neuschäfer
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//
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// Nintendo Wii (Hollywood) GPIO driver
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#include <linux/gpio/driver.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/seq_file.h>
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#include <linux/slab.h>
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/*
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* Register names and offsets courtesy of WiiBrew:
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* https://wiibrew.org/wiki/Hardware/Hollywood_GPIOs
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*
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* Note that for most registers, there are two versions:
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* - HW_GPIOB_* Is always accessible by the Broadway PowerPC core, but does
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* always give access to all GPIO lines
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* - HW_GPIO_* Is only accessible by the Broadway PowerPC code if the memory
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* firewall (AHBPROT) in the Hollywood chipset has been configured to allow
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* such access.
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*
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* The ownership of each GPIO line can be configured in the HW_GPIO_OWNER
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* register: A one bit configures the line for access via the HW_GPIOB_*
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* registers, a zero bit indicates access via HW_GPIO_*. This driver uses
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* HW_GPIOB_*.
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*/
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#define HW_GPIOB_OUT 0x00
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#define HW_GPIOB_DIR 0x04
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#define HW_GPIOB_IN 0x08
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#define HW_GPIOB_INTLVL 0x0c
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#define HW_GPIOB_INTFLAG 0x10
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#define HW_GPIOB_INTMASK 0x14
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#define HW_GPIOB_INMIR 0x18
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#define HW_GPIO_ENABLE 0x1c
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#define HW_GPIO_OUT 0x20
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#define HW_GPIO_DIR 0x24
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#define HW_GPIO_IN 0x28
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#define HW_GPIO_INTLVL 0x2c
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#define HW_GPIO_INTFLAG 0x30
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#define HW_GPIO_INTMASK 0x34
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#define HW_GPIO_INMIR 0x38
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#define HW_GPIO_OWNER 0x3c
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struct hlwd_gpio {
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struct gpio_chip gpioc;
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struct device *dev;
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void __iomem *regs;
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int irq;
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u32 edge_emulation;
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u32 rising_edge, falling_edge;
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};
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static void hlwd_gpio_irqhandler(struct irq_desc *desc)
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{
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struct hlwd_gpio *hlwd =
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gpiochip_get_data(irq_desc_get_handler_data(desc));
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struct irq_chip *chip = irq_desc_get_chip(desc);
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unsigned long flags;
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unsigned long pending;
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int hwirq;
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u32 emulated_pending;
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raw_spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
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pending = ioread32be(hlwd->regs + HW_GPIOB_INTFLAG);
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pending &= ioread32be(hlwd->regs + HW_GPIOB_INTMASK);
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/* Treat interrupts due to edge trigger emulation separately */
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emulated_pending = hlwd->edge_emulation & pending;
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pending &= ~emulated_pending;
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if (emulated_pending) {
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u32 level, rising, falling;
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level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL);
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rising = level & emulated_pending;
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falling = ~level & emulated_pending;
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/* Invert the levels */
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iowrite32be(level ^ emulated_pending,
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hlwd->regs + HW_GPIOB_INTLVL);
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/* Ack all emulated-edge interrupts */
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iowrite32be(emulated_pending, hlwd->regs + HW_GPIOB_INTFLAG);
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/* Signal interrupts only on the correct edge */
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rising &= hlwd->rising_edge;
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falling &= hlwd->falling_edge;
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/* Mark emulated interrupts as pending */
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pending |= rising | falling;
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}
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raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
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chained_irq_enter(chip, desc);
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for_each_set_bit(hwirq, &pending, 32)
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generic_handle_domain_irq(hlwd->gpioc.irq.domain, hwirq);
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chained_irq_exit(chip, desc);
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}
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static void hlwd_gpio_irq_ack(struct irq_data *data)
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{
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struct hlwd_gpio *hlwd =
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gpiochip_get_data(irq_data_get_irq_chip_data(data));
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iowrite32be(BIT(data->hwirq), hlwd->regs + HW_GPIOB_INTFLAG);
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}
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static void hlwd_gpio_irq_mask(struct irq_data *data)
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{
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struct hlwd_gpio *hlwd =
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gpiochip_get_data(irq_data_get_irq_chip_data(data));
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unsigned long flags;
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u32 mask;
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raw_spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
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mask = ioread32be(hlwd->regs + HW_GPIOB_INTMASK);
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mask &= ~BIT(data->hwirq);
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iowrite32be(mask, hlwd->regs + HW_GPIOB_INTMASK);
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raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
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gpiochip_disable_irq(&hlwd->gpioc, irqd_to_hwirq(data));
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}
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static void hlwd_gpio_irq_unmask(struct irq_data *data)
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{
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struct hlwd_gpio *hlwd =
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gpiochip_get_data(irq_data_get_irq_chip_data(data));
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unsigned long flags;
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u32 mask;
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gpiochip_enable_irq(&hlwd->gpioc, irqd_to_hwirq(data));
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raw_spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
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mask = ioread32be(hlwd->regs + HW_GPIOB_INTMASK);
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mask |= BIT(data->hwirq);
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iowrite32be(mask, hlwd->regs + HW_GPIOB_INTMASK);
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raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
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}
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static void hlwd_gpio_irq_enable(struct irq_data *data)
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{
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hlwd_gpio_irq_ack(data);
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hlwd_gpio_irq_unmask(data);
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}
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static void hlwd_gpio_irq_setup_emulation(struct hlwd_gpio *hlwd, int hwirq,
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unsigned int flow_type)
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{
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u32 level, state;
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/* Set the trigger level to the inactive level */
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level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL);
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state = ioread32be(hlwd->regs + HW_GPIOB_IN) & BIT(hwirq);
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level &= ~BIT(hwirq);
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level |= state ^ BIT(hwirq);
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iowrite32be(level, hlwd->regs + HW_GPIOB_INTLVL);
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hlwd->edge_emulation |= BIT(hwirq);
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hlwd->rising_edge &= ~BIT(hwirq);
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hlwd->falling_edge &= ~BIT(hwirq);
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if (flow_type & IRQ_TYPE_EDGE_RISING)
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hlwd->rising_edge |= BIT(hwirq);
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if (flow_type & IRQ_TYPE_EDGE_FALLING)
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hlwd->falling_edge |= BIT(hwirq);
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}
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static int hlwd_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type)
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{
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struct hlwd_gpio *hlwd =
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gpiochip_get_data(irq_data_get_irq_chip_data(data));
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unsigned long flags;
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u32 level;
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raw_spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
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hlwd->edge_emulation &= ~BIT(data->hwirq);
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switch (flow_type) {
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case IRQ_TYPE_LEVEL_HIGH:
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level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL);
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level |= BIT(data->hwirq);
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iowrite32be(level, hlwd->regs + HW_GPIOB_INTLVL);
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break;
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case IRQ_TYPE_LEVEL_LOW:
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level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL);
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level &= ~BIT(data->hwirq);
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iowrite32be(level, hlwd->regs + HW_GPIOB_INTLVL);
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break;
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case IRQ_TYPE_EDGE_RISING:
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case IRQ_TYPE_EDGE_FALLING:
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case IRQ_TYPE_EDGE_BOTH:
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hlwd_gpio_irq_setup_emulation(hlwd, data->hwirq, flow_type);
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break;
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default:
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raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
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return -EINVAL;
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}
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raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
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return 0;
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}
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static void hlwd_gpio_irq_print_chip(struct irq_data *data, struct seq_file *p)
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{
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struct hlwd_gpio *hlwd =
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gpiochip_get_data(irq_data_get_irq_chip_data(data));
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seq_printf(p, dev_name(hlwd->dev));
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}
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static const struct irq_chip hlwd_gpio_irq_chip = {
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.irq_mask = hlwd_gpio_irq_mask,
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.irq_unmask = hlwd_gpio_irq_unmask,
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.irq_enable = hlwd_gpio_irq_enable,
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.irq_set_type = hlwd_gpio_irq_set_type,
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.irq_print_chip = hlwd_gpio_irq_print_chip,
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.flags = IRQCHIP_IMMUTABLE,
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GPIOCHIP_IRQ_RESOURCE_HELPERS,
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};
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static int hlwd_gpio_probe(struct platform_device *pdev)
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{
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struct hlwd_gpio *hlwd;
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u32 ngpios;
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int res;
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hlwd = devm_kzalloc(&pdev->dev, sizeof(*hlwd), GFP_KERNEL);
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if (!hlwd)
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return -ENOMEM;
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hlwd->regs = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(hlwd->regs))
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return PTR_ERR(hlwd->regs);
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hlwd->dev = &pdev->dev;
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/*
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* Claim all GPIOs using the OWNER register. This will not work on
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* systems where the AHBPROT memory firewall hasn't been configured to
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* permit PPC access to HW_GPIO_*.
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*
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* Note that this has to happen before bgpio_init reads the
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* HW_GPIOB_OUT and HW_GPIOB_DIR, because otherwise it reads the wrong
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* values.
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*/
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iowrite32be(0xffffffff, hlwd->regs + HW_GPIO_OWNER);
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res = bgpio_init(&hlwd->gpioc, &pdev->dev, 4,
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hlwd->regs + HW_GPIOB_IN, hlwd->regs + HW_GPIOB_OUT,
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NULL, hlwd->regs + HW_GPIOB_DIR, NULL,
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BGPIOF_BIG_ENDIAN_BYTE_ORDER);
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if (res < 0) {
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dev_warn(&pdev->dev, "bgpio_init failed: %d\n", res);
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return res;
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}
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res = of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios);
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if (res)
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ngpios = 32;
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hlwd->gpioc.ngpio = ngpios;
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/* Mask and ack all interrupts */
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iowrite32be(0, hlwd->regs + HW_GPIOB_INTMASK);
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iowrite32be(0xffffffff, hlwd->regs + HW_GPIOB_INTFLAG);
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/*
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* If this GPIO controller is not marked as an interrupt controller in
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* the DT, skip interrupt support.
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*/
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if (of_property_read_bool(pdev->dev.of_node, "interrupt-controller")) {
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struct gpio_irq_chip *girq;
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hlwd->irq = platform_get_irq(pdev, 0);
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if (hlwd->irq < 0) {
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dev_info(&pdev->dev, "platform_get_irq returned %d\n",
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hlwd->irq);
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return hlwd->irq;
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}
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girq = &hlwd->gpioc.irq;
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gpio_irq_chip_set_chip(girq, &hlwd_gpio_irq_chip);
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girq->parent_handler = hlwd_gpio_irqhandler;
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girq->num_parents = 1;
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girq->parents = devm_kcalloc(&pdev->dev, 1,
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sizeof(*girq->parents),
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GFP_KERNEL);
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if (!girq->parents)
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return -ENOMEM;
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girq->parents[0] = hlwd->irq;
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girq->default_type = IRQ_TYPE_NONE;
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girq->handler = handle_level_irq;
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}
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return devm_gpiochip_add_data(&pdev->dev, &hlwd->gpioc, hlwd);
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}
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static const struct of_device_id hlwd_gpio_match[] = {
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{ .compatible = "nintendo,hollywood-gpio", },
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{},
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};
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MODULE_DEVICE_TABLE(of, hlwd_gpio_match);
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static struct platform_driver hlwd_gpio_driver = {
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.driver = {
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.name = "gpio-hlwd",
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.of_match_table = hlwd_gpio_match,
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},
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.probe = hlwd_gpio_probe,
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};
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module_platform_driver(hlwd_gpio_driver);
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MODULE_AUTHOR("Jonathan Neuschäfer <j.neuschaefer@gmx.net>");
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MODULE_DESCRIPTION("Nintendo Wii GPIO driver");
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MODULE_LICENSE("GPL");
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