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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-26 19:00:25 +00:00
![Rob Herring](/assets/img/avatar_default.png)
The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Acked-by: Romain Perier <romain.perier@gmail.com> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
496 lines
13 KiB
C
496 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0
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//
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// Copyright (C) 2017 Socionext Inc.
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// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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#include <linux/bits.h>
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#include <linux/gpio/driver.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#include <dt-bindings/gpio/uniphier-gpio.h>
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#define UNIPHIER_GPIO_IRQ_MAX_NUM 24
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#define UNIPHIER_GPIO_PORT_DATA 0x0 /* data */
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#define UNIPHIER_GPIO_PORT_DIR 0x4 /* direction (1:in, 0:out) */
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#define UNIPHIER_GPIO_IRQ_EN 0x90 /* irq enable */
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#define UNIPHIER_GPIO_IRQ_MODE 0x94 /* irq mode (1: both edge) */
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#define UNIPHIER_GPIO_IRQ_FLT_EN 0x98 /* noise filter enable */
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#define UNIPHIER_GPIO_IRQ_FLT_CYC 0x9c /* noise filter clock cycle */
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struct uniphier_gpio_priv {
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struct gpio_chip chip;
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struct irq_chip irq_chip;
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struct irq_domain *domain;
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void __iomem *regs;
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spinlock_t lock;
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u32 saved_vals[];
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};
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static unsigned int uniphier_gpio_bank_to_reg(unsigned int bank)
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{
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unsigned int reg;
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reg = (bank + 1) * 8;
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/*
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* Unfortunately, the GPIO port registers are not contiguous because
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* offset 0x90-0x9f is used for IRQ. Add 0x10 when crossing the region.
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*/
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if (reg >= UNIPHIER_GPIO_IRQ_EN)
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reg += 0x10;
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return reg;
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}
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static void uniphier_gpio_get_bank_and_mask(unsigned int offset,
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unsigned int *bank, u32 *mask)
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{
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*bank = offset / UNIPHIER_GPIO_LINES_PER_BANK;
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*mask = BIT(offset % UNIPHIER_GPIO_LINES_PER_BANK);
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}
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static void uniphier_gpio_reg_update(struct uniphier_gpio_priv *priv,
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unsigned int reg, u32 mask, u32 val)
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{
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unsigned long flags;
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u32 tmp;
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spin_lock_irqsave(&priv->lock, flags);
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tmp = readl(priv->regs + reg);
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tmp &= ~mask;
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tmp |= mask & val;
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writel(tmp, priv->regs + reg);
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spin_unlock_irqrestore(&priv->lock, flags);
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}
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static void uniphier_gpio_bank_write(struct gpio_chip *chip, unsigned int bank,
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unsigned int reg, u32 mask, u32 val)
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{
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struct uniphier_gpio_priv *priv = gpiochip_get_data(chip);
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if (!mask)
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return;
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uniphier_gpio_reg_update(priv, uniphier_gpio_bank_to_reg(bank) + reg,
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mask, val);
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}
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static void uniphier_gpio_offset_write(struct gpio_chip *chip,
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unsigned int offset, unsigned int reg,
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int val)
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{
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unsigned int bank;
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u32 mask;
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uniphier_gpio_get_bank_and_mask(offset, &bank, &mask);
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uniphier_gpio_bank_write(chip, bank, reg, mask, val ? mask : 0);
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}
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static int uniphier_gpio_offset_read(struct gpio_chip *chip,
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unsigned int offset, unsigned int reg)
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{
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struct uniphier_gpio_priv *priv = gpiochip_get_data(chip);
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unsigned int bank, reg_offset;
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u32 mask;
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uniphier_gpio_get_bank_and_mask(offset, &bank, &mask);
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reg_offset = uniphier_gpio_bank_to_reg(bank) + reg;
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return !!(readl(priv->regs + reg_offset) & mask);
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}
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static int uniphier_gpio_get_direction(struct gpio_chip *chip,
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unsigned int offset)
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{
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if (uniphier_gpio_offset_read(chip, offset, UNIPHIER_GPIO_PORT_DIR))
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return GPIO_LINE_DIRECTION_IN;
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return GPIO_LINE_DIRECTION_OUT;
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}
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static int uniphier_gpio_direction_input(struct gpio_chip *chip,
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unsigned int offset)
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{
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uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DIR, 1);
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return 0;
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}
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static int uniphier_gpio_direction_output(struct gpio_chip *chip,
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unsigned int offset, int val)
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{
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uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DATA, val);
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uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DIR, 0);
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return 0;
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}
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static int uniphier_gpio_get(struct gpio_chip *chip, unsigned int offset)
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{
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return uniphier_gpio_offset_read(chip, offset, UNIPHIER_GPIO_PORT_DATA);
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}
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static void uniphier_gpio_set(struct gpio_chip *chip,
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unsigned int offset, int val)
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{
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uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DATA, val);
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}
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static void uniphier_gpio_set_multiple(struct gpio_chip *chip,
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unsigned long *mask, unsigned long *bits)
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{
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unsigned long i, bank, bank_mask, bank_bits;
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for_each_set_clump8(i, bank_mask, mask, chip->ngpio) {
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bank = i / UNIPHIER_GPIO_LINES_PER_BANK;
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bank_bits = bitmap_get_value8(bits, i);
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uniphier_gpio_bank_write(chip, bank, UNIPHIER_GPIO_PORT_DATA,
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bank_mask, bank_bits);
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}
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}
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static int uniphier_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
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{
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struct irq_fwspec fwspec;
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if (offset < UNIPHIER_GPIO_IRQ_OFFSET)
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return -ENXIO;
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fwspec.fwnode = of_node_to_fwnode(chip->parent->of_node);
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fwspec.param_count = 2;
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fwspec.param[0] = offset - UNIPHIER_GPIO_IRQ_OFFSET;
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/*
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* IRQ_TYPE_NONE is rejected by the parent irq domain. Set LEVEL_HIGH
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* temporarily. Anyway, ->irq_set_type() will override it later.
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*/
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fwspec.param[1] = IRQ_TYPE_LEVEL_HIGH;
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return irq_create_fwspec_mapping(&fwspec);
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}
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static void uniphier_gpio_irq_mask(struct irq_data *data)
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{
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struct uniphier_gpio_priv *priv = irq_data_get_irq_chip_data(data);
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u32 mask = BIT(irqd_to_hwirq(data));
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uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_EN, mask, 0);
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irq_chip_mask_parent(data);
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}
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static void uniphier_gpio_irq_unmask(struct irq_data *data)
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{
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struct uniphier_gpio_priv *priv = irq_data_get_irq_chip_data(data);
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u32 mask = BIT(irqd_to_hwirq(data));
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uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_EN, mask, mask);
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irq_chip_unmask_parent(data);
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}
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static int uniphier_gpio_irq_set_type(struct irq_data *data, unsigned int type)
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{
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struct uniphier_gpio_priv *priv = irq_data_get_irq_chip_data(data);
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u32 mask = BIT(irqd_to_hwirq(data));
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u32 val = 0;
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if (type == IRQ_TYPE_EDGE_BOTH) {
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val = mask;
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type = IRQ_TYPE_EDGE_FALLING;
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}
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uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_MODE, mask, val);
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/* To enable both edge detection, the noise filter must be enabled. */
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uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_FLT_EN, mask, val);
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return irq_chip_set_type_parent(data, type);
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}
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static int uniphier_gpio_irq_get_parent_hwirq(struct uniphier_gpio_priv *priv,
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unsigned int hwirq)
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{
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struct device_node *np = priv->chip.parent->of_node;
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const __be32 *range;
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u32 base, parent_base, size;
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int len;
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range = of_get_property(np, "socionext,interrupt-ranges", &len);
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if (!range)
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return -EINVAL;
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len /= sizeof(*range);
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for (; len >= 3; len -= 3) {
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base = be32_to_cpu(*range++);
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parent_base = be32_to_cpu(*range++);
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size = be32_to_cpu(*range++);
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if (base <= hwirq && hwirq < base + size)
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return hwirq - base + parent_base;
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}
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return -ENOENT;
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}
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static int uniphier_gpio_irq_domain_translate(struct irq_domain *domain,
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struct irq_fwspec *fwspec,
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unsigned long *out_hwirq,
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unsigned int *out_type)
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{
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if (WARN_ON(fwspec->param_count < 2))
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return -EINVAL;
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*out_hwirq = fwspec->param[0];
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*out_type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
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return 0;
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}
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static int uniphier_gpio_irq_domain_alloc(struct irq_domain *domain,
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unsigned int virq,
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unsigned int nr_irqs, void *arg)
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{
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struct uniphier_gpio_priv *priv = domain->host_data;
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struct irq_fwspec parent_fwspec;
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irq_hw_number_t hwirq;
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unsigned int type;
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int ret;
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if (WARN_ON(nr_irqs != 1))
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return -EINVAL;
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ret = uniphier_gpio_irq_domain_translate(domain, arg, &hwirq, &type);
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if (ret)
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return ret;
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ret = uniphier_gpio_irq_get_parent_hwirq(priv, hwirq);
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if (ret < 0)
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return ret;
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/* parent is UniPhier AIDET */
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parent_fwspec.fwnode = domain->parent->fwnode;
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parent_fwspec.param_count = 2;
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parent_fwspec.param[0] = ret;
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parent_fwspec.param[1] = (type == IRQ_TYPE_EDGE_BOTH) ?
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IRQ_TYPE_EDGE_FALLING : type;
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ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
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&priv->irq_chip, priv);
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if (ret)
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return ret;
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return irq_domain_alloc_irqs_parent(domain, virq, 1, &parent_fwspec);
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}
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static int uniphier_gpio_irq_domain_activate(struct irq_domain *domain,
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struct irq_data *data, bool early)
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{
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struct uniphier_gpio_priv *priv = domain->host_data;
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struct gpio_chip *chip = &priv->chip;
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return gpiochip_lock_as_irq(chip,
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irqd_to_hwirq(data) + UNIPHIER_GPIO_IRQ_OFFSET);
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}
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static void uniphier_gpio_irq_domain_deactivate(struct irq_domain *domain,
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struct irq_data *data)
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{
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struct uniphier_gpio_priv *priv = domain->host_data;
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struct gpio_chip *chip = &priv->chip;
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gpiochip_unlock_as_irq(chip,
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irqd_to_hwirq(data) + UNIPHIER_GPIO_IRQ_OFFSET);
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}
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static const struct irq_domain_ops uniphier_gpio_irq_domain_ops = {
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.alloc = uniphier_gpio_irq_domain_alloc,
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.free = irq_domain_free_irqs_common,
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.activate = uniphier_gpio_irq_domain_activate,
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.deactivate = uniphier_gpio_irq_domain_deactivate,
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.translate = uniphier_gpio_irq_domain_translate,
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};
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static void uniphier_gpio_hw_init(struct uniphier_gpio_priv *priv)
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{
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/*
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* Due to the hardware design, the noise filter must be enabled to
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* detect both edge interrupts. This filter is intended to remove the
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* noise from the irq lines. It does not work for GPIO input, so GPIO
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* debounce is not supported. Unfortunately, the filter period is
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* shared among all irq lines. Just choose a sensible period here.
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*/
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writel(0xff, priv->regs + UNIPHIER_GPIO_IRQ_FLT_CYC);
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}
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static unsigned int uniphier_gpio_get_nbanks(unsigned int ngpio)
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{
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return DIV_ROUND_UP(ngpio, UNIPHIER_GPIO_LINES_PER_BANK);
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}
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static int uniphier_gpio_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device_node *parent_np;
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struct irq_domain *parent_domain;
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struct uniphier_gpio_priv *priv;
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struct gpio_chip *chip;
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struct irq_chip *irq_chip;
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unsigned int nregs;
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u32 ngpios;
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int ret;
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parent_np = of_irq_find_parent(dev->of_node);
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if (!parent_np)
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return -ENXIO;
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parent_domain = irq_find_host(parent_np);
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of_node_put(parent_np);
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if (!parent_domain)
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return -EPROBE_DEFER;
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ret = of_property_read_u32(dev->of_node, "ngpios", &ngpios);
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if (ret)
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return ret;
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nregs = uniphier_gpio_get_nbanks(ngpios) * 2 + 3;
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priv = devm_kzalloc(dev, struct_size(priv, saved_vals, nregs),
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GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->regs = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(priv->regs))
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return PTR_ERR(priv->regs);
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spin_lock_init(&priv->lock);
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chip = &priv->chip;
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chip->label = dev_name(dev);
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chip->parent = dev;
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chip->request = gpiochip_generic_request;
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chip->free = gpiochip_generic_free;
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chip->get_direction = uniphier_gpio_get_direction;
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chip->direction_input = uniphier_gpio_direction_input;
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chip->direction_output = uniphier_gpio_direction_output;
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chip->get = uniphier_gpio_get;
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chip->set = uniphier_gpio_set;
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chip->set_multiple = uniphier_gpio_set_multiple;
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chip->to_irq = uniphier_gpio_to_irq;
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chip->base = -1;
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chip->ngpio = ngpios;
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irq_chip = &priv->irq_chip;
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irq_chip->name = dev_name(dev);
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irq_chip->irq_mask = uniphier_gpio_irq_mask;
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irq_chip->irq_unmask = uniphier_gpio_irq_unmask;
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irq_chip->irq_eoi = irq_chip_eoi_parent;
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irq_chip->irq_set_affinity = irq_chip_set_affinity_parent;
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irq_chip->irq_set_type = uniphier_gpio_irq_set_type;
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uniphier_gpio_hw_init(priv);
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ret = devm_gpiochip_add_data(dev, chip, priv);
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if (ret)
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return ret;
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priv->domain = irq_domain_create_hierarchy(
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parent_domain, 0,
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UNIPHIER_GPIO_IRQ_MAX_NUM,
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of_node_to_fwnode(dev->of_node),
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&uniphier_gpio_irq_domain_ops, priv);
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if (!priv->domain)
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return -ENOMEM;
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platform_set_drvdata(pdev, priv);
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return 0;
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}
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static int uniphier_gpio_remove(struct platform_device *pdev)
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{
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struct uniphier_gpio_priv *priv = platform_get_drvdata(pdev);
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irq_domain_remove(priv->domain);
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return 0;
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}
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static int __maybe_unused uniphier_gpio_suspend(struct device *dev)
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{
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struct uniphier_gpio_priv *priv = dev_get_drvdata(dev);
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unsigned int nbanks = uniphier_gpio_get_nbanks(priv->chip.ngpio);
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u32 *val = priv->saved_vals;
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unsigned int reg;
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int i;
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for (i = 0; i < nbanks; i++) {
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reg = uniphier_gpio_bank_to_reg(i);
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*val++ = readl(priv->regs + reg + UNIPHIER_GPIO_PORT_DATA);
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*val++ = readl(priv->regs + reg + UNIPHIER_GPIO_PORT_DIR);
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}
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*val++ = readl(priv->regs + UNIPHIER_GPIO_IRQ_EN);
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*val++ = readl(priv->regs + UNIPHIER_GPIO_IRQ_MODE);
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*val++ = readl(priv->regs + UNIPHIER_GPIO_IRQ_FLT_EN);
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return 0;
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}
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static int __maybe_unused uniphier_gpio_resume(struct device *dev)
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{
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struct uniphier_gpio_priv *priv = dev_get_drvdata(dev);
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unsigned int nbanks = uniphier_gpio_get_nbanks(priv->chip.ngpio);
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const u32 *val = priv->saved_vals;
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unsigned int reg;
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int i;
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for (i = 0; i < nbanks; i++) {
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reg = uniphier_gpio_bank_to_reg(i);
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writel(*val++, priv->regs + reg + UNIPHIER_GPIO_PORT_DATA);
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writel(*val++, priv->regs + reg + UNIPHIER_GPIO_PORT_DIR);
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}
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writel(*val++, priv->regs + UNIPHIER_GPIO_IRQ_EN);
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writel(*val++, priv->regs + UNIPHIER_GPIO_IRQ_MODE);
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writel(*val++, priv->regs + UNIPHIER_GPIO_IRQ_FLT_EN);
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uniphier_gpio_hw_init(priv);
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return 0;
|
|
}
|
|
|
|
static const struct dev_pm_ops uniphier_gpio_pm_ops = {
|
|
SET_LATE_SYSTEM_SLEEP_PM_OPS(uniphier_gpio_suspend,
|
|
uniphier_gpio_resume)
|
|
};
|
|
|
|
static const struct of_device_id uniphier_gpio_match[] = {
|
|
{ .compatible = "socionext,uniphier-gpio" },
|
|
{ /* sentinel */ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, uniphier_gpio_match);
|
|
|
|
static struct platform_driver uniphier_gpio_driver = {
|
|
.probe = uniphier_gpio_probe,
|
|
.remove = uniphier_gpio_remove,
|
|
.driver = {
|
|
.name = "uniphier-gpio",
|
|
.of_match_table = uniphier_gpio_match,
|
|
.pm = &uniphier_gpio_pm_ops,
|
|
},
|
|
};
|
|
module_platform_driver(uniphier_gpio_driver);
|
|
|
|
MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
|
|
MODULE_DESCRIPTION("UniPhier GPIO driver");
|
|
MODULE_LICENSE("GPL v2");
|