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![Linus Walleij](/assets/img/avatar_default.png)
Convert the driver to immutable irq-chip with a bit of intuition. The driver is for a hierarchical chip so some extra care needs to be taken to introduce two new callbacks. Cc: Marc Zyngier <maz@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
232 lines
5.7 KiB
C
232 lines
5.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Toshiba Visconti GPIO Support
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*
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* (C) Copyright 2020 Toshiba Electronic Devices & Storage Corporation
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* (C) Copyright 2020 TOSHIBA CORPORATION
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*
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* Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
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*/
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#include <linux/gpio/driver.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/io.h>
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#include <linux/of_irq.h>
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#include <linux/platform_device.h>
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#include <linux/seq_file.h>
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#include <linux/bitops.h>
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/* register offset */
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#define GPIO_DIR 0x00
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#define GPIO_IDATA 0x08
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#define GPIO_ODATA 0x10
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#define GPIO_OSET 0x18
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#define GPIO_OCLR 0x20
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#define GPIO_INTMODE 0x30
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#define BASE_HW_IRQ 24
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struct visconti_gpio {
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void __iomem *base;
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spinlock_t lock; /* protect gpio register */
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struct gpio_chip gpio_chip;
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struct device *dev;
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};
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static int visconti_gpio_irq_set_type(struct irq_data *d, unsigned int type)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct visconti_gpio *priv = gpiochip_get_data(gc);
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u32 offset = irqd_to_hwirq(d);
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u32 bit = BIT(offset);
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u32 intc_type = IRQ_TYPE_EDGE_RISING;
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u32 intmode, odata;
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int ret = 0;
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unsigned long flags;
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spin_lock_irqsave(&priv->lock, flags);
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odata = readl(priv->base + GPIO_ODATA);
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intmode = readl(priv->base + GPIO_INTMODE);
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switch (type) {
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case IRQ_TYPE_EDGE_RISING:
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odata &= ~bit;
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intmode &= ~bit;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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odata |= bit;
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intmode &= ~bit;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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intmode |= bit;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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intc_type = IRQ_TYPE_LEVEL_HIGH;
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odata &= ~bit;
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intmode &= ~bit;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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intc_type = IRQ_TYPE_LEVEL_HIGH;
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odata |= bit;
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intmode &= ~bit;
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break;
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default:
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ret = -EINVAL;
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goto err;
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}
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writel(odata, priv->base + GPIO_ODATA);
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writel(intmode, priv->base + GPIO_INTMODE);
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irq_set_irq_type(offset, intc_type);
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ret = irq_chip_set_type_parent(d, type);
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err:
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spin_unlock_irqrestore(&priv->lock, flags);
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return ret;
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}
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static int visconti_gpio_child_to_parent_hwirq(struct gpio_chip *gc,
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unsigned int child,
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unsigned int child_type,
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unsigned int *parent,
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unsigned int *parent_type)
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{
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/* Interrupts 0..15 mapped to interrupts 24..39 on the GIC */
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if (child < 16) {
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/* All these interrupts are level high in the CPU */
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*parent_type = IRQ_TYPE_LEVEL_HIGH;
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*parent = child + BASE_HW_IRQ;
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return 0;
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}
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return -EINVAL;
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}
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static int visconti_gpio_populate_parent_fwspec(struct gpio_chip *chip,
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union gpio_irq_fwspec *gfwspec,
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unsigned int parent_hwirq,
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unsigned int parent_type)
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{
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struct irq_fwspec *fwspec = &gfwspec->fwspec;
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fwspec->fwnode = chip->irq.parent_domain->fwnode;
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fwspec->param_count = 3;
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fwspec->param[0] = 0;
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fwspec->param[1] = parent_hwirq;
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fwspec->param[2] = parent_type;
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return 0;
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}
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static void visconti_gpio_mask_irq(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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irq_chip_mask_parent(d);
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gpiochip_disable_irq(gc, irqd_to_hwirq(d));
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}
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static void visconti_gpio_unmask_irq(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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gpiochip_enable_irq(gc, irqd_to_hwirq(d));
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irq_chip_unmask_parent(d);
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}
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static void visconti_gpio_irq_print_chip(struct irq_data *d, struct seq_file *p)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct visconti_gpio *priv = gpiochip_get_data(gc);
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seq_printf(p, dev_name(priv->dev));
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}
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static const struct irq_chip visconti_gpio_irq_chip = {
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.irq_mask = visconti_gpio_mask_irq,
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.irq_unmask = visconti_gpio_unmask_irq,
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.irq_eoi = irq_chip_eoi_parent,
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.irq_set_type = visconti_gpio_irq_set_type,
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.irq_print_chip = visconti_gpio_irq_print_chip,
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.flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_MASK_ON_SUSPEND |
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IRQCHIP_IMMUTABLE,
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GPIOCHIP_IRQ_RESOURCE_HELPERS,
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};
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static int visconti_gpio_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct visconti_gpio *priv;
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struct gpio_irq_chip *girq;
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struct irq_domain *parent;
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struct device_node *irq_parent;
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int ret;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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spin_lock_init(&priv->lock);
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priv->dev = dev;
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priv->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(priv->base))
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return PTR_ERR(priv->base);
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irq_parent = of_irq_find_parent(dev->of_node);
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if (!irq_parent) {
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dev_err(dev, "No IRQ parent node\n");
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return -ENODEV;
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}
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parent = irq_find_host(irq_parent);
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of_node_put(irq_parent);
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if (!parent) {
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dev_err(dev, "No IRQ parent domain\n");
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return -ENODEV;
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}
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ret = bgpio_init(&priv->gpio_chip, dev, 4,
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priv->base + GPIO_IDATA,
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priv->base + GPIO_OSET,
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priv->base + GPIO_OCLR,
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priv->base + GPIO_DIR,
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NULL,
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0);
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if (ret) {
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dev_err(dev, "unable to init generic GPIO\n");
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return ret;
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}
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girq = &priv->gpio_chip.irq;
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gpio_irq_chip_set_chip(girq, &visconti_gpio_irq_chip);
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girq->fwnode = of_node_to_fwnode(dev->of_node);
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girq->parent_domain = parent;
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girq->child_to_parent_hwirq = visconti_gpio_child_to_parent_hwirq;
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girq->populate_parent_alloc_arg = visconti_gpio_populate_parent_fwspec;
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girq->default_type = IRQ_TYPE_NONE;
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girq->handler = handle_level_irq;
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return devm_gpiochip_add_data(dev, &priv->gpio_chip, priv);
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}
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static const struct of_device_id visconti_gpio_of_match[] = {
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{ .compatible = "toshiba,gpio-tmpv7708", },
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{ /* end of table */ }
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};
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MODULE_DEVICE_TABLE(of, visconti_gpio_of_match);
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static struct platform_driver visconti_gpio_driver = {
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.probe = visconti_gpio_probe,
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.driver = {
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.name = "visconti_gpio",
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.of_match_table = visconti_gpio_of_match,
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}
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};
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module_platform_driver(visconti_gpio_driver);
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MODULE_AUTHOR("Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>");
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MODULE_DESCRIPTION("Toshiba Visconti GPIO Driver");
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MODULE_LICENSE("GPL v2");
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