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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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![Rob Herring](/assets/img/avatar_default.png)
The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Acked-by: Romain Perier <romain.perier@gmail.com> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
741 lines
20 KiB
C
741 lines
20 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Xilinx gpio driver for xps/axi_gpio IP.
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*
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* Copyright 2008 - 2013 Xilinx, Inc.
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*/
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#include <linux/bitmap.h>
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/errno.h>
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#include <linux/gpio/driver.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/slab.h>
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/* Register Offset Definitions */
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#define XGPIO_DATA_OFFSET (0x0) /* Data register */
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#define XGPIO_TRI_OFFSET (0x4) /* I/O direction register */
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#define XGPIO_CHANNEL0_OFFSET 0x0
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#define XGPIO_CHANNEL1_OFFSET 0x8
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#define XGPIO_GIER_OFFSET 0x11c /* Global Interrupt Enable */
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#define XGPIO_GIER_IE BIT(31)
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#define XGPIO_IPISR_OFFSET 0x120 /* IP Interrupt Status */
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#define XGPIO_IPIER_OFFSET 0x128 /* IP Interrupt Enable */
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/* Read/Write access to the GPIO registers */
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#if defined(CONFIG_ARCH_ZYNQ) || defined(CONFIG_X86)
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# define xgpio_readreg(offset) readl(offset)
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# define xgpio_writereg(offset, val) writel(val, offset)
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#else
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# define xgpio_readreg(offset) __raw_readl(offset)
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# define xgpio_writereg(offset, val) __raw_writel(val, offset)
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#endif
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/**
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* struct xgpio_instance - Stores information about GPIO device
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* @gc: GPIO chip
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* @regs: register block
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* @hw_map: GPIO pin mapping on hardware side
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* @sw_map: GPIO pin mapping on software side
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* @state: GPIO write state shadow register
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* @last_irq_read: GPIO read state register from last interrupt
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* @dir: GPIO direction shadow register
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* @gpio_lock: Lock used for synchronization
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* @irq: IRQ used by GPIO device
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* @irqchip: IRQ chip
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* @enable: GPIO IRQ enable/disable bitfield
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* @rising_edge: GPIO IRQ rising edge enable/disable bitfield
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* @falling_edge: GPIO IRQ falling edge enable/disable bitfield
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* @clk: clock resource for this driver
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*/
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struct xgpio_instance {
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struct gpio_chip gc;
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void __iomem *regs;
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DECLARE_BITMAP(hw_map, 64);
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DECLARE_BITMAP(sw_map, 64);
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DECLARE_BITMAP(state, 64);
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DECLARE_BITMAP(last_irq_read, 64);
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DECLARE_BITMAP(dir, 64);
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spinlock_t gpio_lock; /* For serializing operations */
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int irq;
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DECLARE_BITMAP(enable, 64);
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DECLARE_BITMAP(rising_edge, 64);
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DECLARE_BITMAP(falling_edge, 64);
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struct clk *clk;
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};
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static inline int xgpio_from_bit(struct xgpio_instance *chip, int bit)
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{
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return bitmap_bitremap(bit, chip->hw_map, chip->sw_map, 64);
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}
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static inline int xgpio_to_bit(struct xgpio_instance *chip, int gpio)
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{
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return bitmap_bitremap(gpio, chip->sw_map, chip->hw_map, 64);
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}
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static inline u32 xgpio_get_value32(const unsigned long *map, int bit)
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{
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const size_t index = BIT_WORD(bit);
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const unsigned long offset = (bit % BITS_PER_LONG) & BIT(5);
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return (map[index] >> offset) & 0xFFFFFFFFul;
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}
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static inline void xgpio_set_value32(unsigned long *map, int bit, u32 v)
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{
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const size_t index = BIT_WORD(bit);
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const unsigned long offset = (bit % BITS_PER_LONG) & BIT(5);
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map[index] &= ~(0xFFFFFFFFul << offset);
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map[index] |= (unsigned long)v << offset;
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}
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static inline int xgpio_regoffset(struct xgpio_instance *chip, int ch)
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{
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switch (ch) {
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case 0:
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return XGPIO_CHANNEL0_OFFSET;
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case 1:
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return XGPIO_CHANNEL1_OFFSET;
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default:
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return -EINVAL;
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}
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}
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static void xgpio_read_ch(struct xgpio_instance *chip, int reg, int bit, unsigned long *a)
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{
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void __iomem *addr = chip->regs + reg + xgpio_regoffset(chip, bit / 32);
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xgpio_set_value32(a, bit, xgpio_readreg(addr));
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}
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static void xgpio_write_ch(struct xgpio_instance *chip, int reg, int bit, unsigned long *a)
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{
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void __iomem *addr = chip->regs + reg + xgpio_regoffset(chip, bit / 32);
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xgpio_writereg(addr, xgpio_get_value32(a, bit));
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}
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static void xgpio_read_ch_all(struct xgpio_instance *chip, int reg, unsigned long *a)
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{
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int bit, lastbit = xgpio_to_bit(chip, chip->gc.ngpio - 1);
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for (bit = 0; bit <= lastbit ; bit += 32)
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xgpio_read_ch(chip, reg, bit, a);
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}
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static void xgpio_write_ch_all(struct xgpio_instance *chip, int reg, unsigned long *a)
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{
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int bit, lastbit = xgpio_to_bit(chip, chip->gc.ngpio - 1);
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for (bit = 0; bit <= lastbit ; bit += 32)
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xgpio_write_ch(chip, reg, bit, a);
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}
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/**
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* xgpio_get - Read the specified signal of the GPIO device.
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* @gc: Pointer to gpio_chip device structure.
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* @gpio: GPIO signal number.
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*
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* This function reads the specified signal of the GPIO device.
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*
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* Return:
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* 0 if direction of GPIO signals is set as input otherwise it
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* returns negative error value.
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*/
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static int xgpio_get(struct gpio_chip *gc, unsigned int gpio)
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{
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struct xgpio_instance *chip = gpiochip_get_data(gc);
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int bit = xgpio_to_bit(chip, gpio);
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DECLARE_BITMAP(state, 64);
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xgpio_read_ch(chip, XGPIO_DATA_OFFSET, bit, state);
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return test_bit(bit, state);
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}
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/**
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* xgpio_set - Write the specified signal of the GPIO device.
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* @gc: Pointer to gpio_chip device structure.
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* @gpio: GPIO signal number.
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* @val: Value to be written to specified signal.
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*
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* This function writes the specified value in to the specified signal of the
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* GPIO device.
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*/
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static void xgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
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{
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unsigned long flags;
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struct xgpio_instance *chip = gpiochip_get_data(gc);
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int bit = xgpio_to_bit(chip, gpio);
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spin_lock_irqsave(&chip->gpio_lock, flags);
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/* Write to GPIO signal and set its direction to output */
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__assign_bit(bit, chip->state, val);
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xgpio_write_ch(chip, XGPIO_DATA_OFFSET, bit, chip->state);
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spin_unlock_irqrestore(&chip->gpio_lock, flags);
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}
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/**
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* xgpio_set_multiple - Write the specified signals of the GPIO device.
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* @gc: Pointer to gpio_chip device structure.
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* @mask: Mask of the GPIOS to modify.
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* @bits: Value to be wrote on each GPIO
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*
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* This function writes the specified values into the specified signals of the
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* GPIO devices.
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*/
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static void xgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
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unsigned long *bits)
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{
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DECLARE_BITMAP(hw_mask, 64);
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DECLARE_BITMAP(hw_bits, 64);
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DECLARE_BITMAP(state, 64);
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unsigned long flags;
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struct xgpio_instance *chip = gpiochip_get_data(gc);
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bitmap_remap(hw_mask, mask, chip->sw_map, chip->hw_map, 64);
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bitmap_remap(hw_bits, bits, chip->sw_map, chip->hw_map, 64);
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spin_lock_irqsave(&chip->gpio_lock, flags);
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bitmap_replace(state, chip->state, hw_bits, hw_mask, 64);
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xgpio_write_ch_all(chip, XGPIO_DATA_OFFSET, state);
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bitmap_copy(chip->state, state, 64);
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spin_unlock_irqrestore(&chip->gpio_lock, flags);
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}
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/**
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* xgpio_dir_in - Set the direction of the specified GPIO signal as input.
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* @gc: Pointer to gpio_chip device structure.
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* @gpio: GPIO signal number.
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*
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* Return:
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* 0 - if direction of GPIO signals is set as input
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* otherwise it returns negative error value.
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*/
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static int xgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
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{
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unsigned long flags;
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struct xgpio_instance *chip = gpiochip_get_data(gc);
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int bit = xgpio_to_bit(chip, gpio);
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spin_lock_irqsave(&chip->gpio_lock, flags);
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/* Set the GPIO bit in shadow register and set direction as input */
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__set_bit(bit, chip->dir);
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xgpio_write_ch(chip, XGPIO_TRI_OFFSET, bit, chip->dir);
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spin_unlock_irqrestore(&chip->gpio_lock, flags);
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return 0;
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}
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/**
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* xgpio_dir_out - Set the direction of the specified GPIO signal as output.
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* @gc: Pointer to gpio_chip device structure.
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* @gpio: GPIO signal number.
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* @val: Value to be written to specified signal.
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*
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* This function sets the direction of specified GPIO signal as output.
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*
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* Return:
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* If all GPIO signals of GPIO chip is configured as input then it returns
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* error otherwise it returns 0.
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*/
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static int xgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
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{
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unsigned long flags;
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struct xgpio_instance *chip = gpiochip_get_data(gc);
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int bit = xgpio_to_bit(chip, gpio);
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spin_lock_irqsave(&chip->gpio_lock, flags);
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/* Write state of GPIO signal */
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__assign_bit(bit, chip->state, val);
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xgpio_write_ch(chip, XGPIO_DATA_OFFSET, bit, chip->state);
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/* Clear the GPIO bit in shadow register and set direction as output */
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__clear_bit(bit, chip->dir);
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xgpio_write_ch(chip, XGPIO_TRI_OFFSET, bit, chip->dir);
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spin_unlock_irqrestore(&chip->gpio_lock, flags);
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return 0;
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}
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/**
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* xgpio_save_regs - Set initial values of GPIO pins
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* @chip: Pointer to GPIO instance
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*/
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static void xgpio_save_regs(struct xgpio_instance *chip)
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{
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xgpio_write_ch_all(chip, XGPIO_DATA_OFFSET, chip->state);
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xgpio_write_ch_all(chip, XGPIO_TRI_OFFSET, chip->dir);
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}
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static int xgpio_request(struct gpio_chip *chip, unsigned int offset)
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{
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int ret;
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ret = pm_runtime_get_sync(chip->parent);
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/*
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* If the device is already active pm_runtime_get() will return 1 on
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* success, but gpio_request still needs to return 0.
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*/
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return ret < 0 ? ret : 0;
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}
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static void xgpio_free(struct gpio_chip *chip, unsigned int offset)
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{
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pm_runtime_put(chip->parent);
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}
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static int __maybe_unused xgpio_suspend(struct device *dev)
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{
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struct xgpio_instance *gpio = dev_get_drvdata(dev);
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struct irq_data *data = irq_get_irq_data(gpio->irq);
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if (!data) {
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dev_dbg(dev, "IRQ not connected\n");
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return pm_runtime_force_suspend(dev);
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}
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if (!irqd_is_wakeup_set(data))
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return pm_runtime_force_suspend(dev);
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return 0;
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}
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/**
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* xgpio_remove - Remove method for the GPIO device.
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* @pdev: pointer to the platform device
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*
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* This function remove gpiochips and frees all the allocated resources.
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*
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* Return: 0 always
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*/
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static int xgpio_remove(struct platform_device *pdev)
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{
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struct xgpio_instance *gpio = platform_get_drvdata(pdev);
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pm_runtime_get_sync(&pdev->dev);
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pm_runtime_put_noidle(&pdev->dev);
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pm_runtime_disable(&pdev->dev);
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clk_disable_unprepare(gpio->clk);
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return 0;
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}
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/**
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* xgpio_irq_ack - Acknowledge a child GPIO interrupt.
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* @irq_data: per IRQ and chip data passed down to chip functions
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* This currently does nothing, but irq_ack is unconditionally called by
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* handle_edge_irq and therefore must be defined.
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*/
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static void xgpio_irq_ack(struct irq_data *irq_data)
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{
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}
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static int __maybe_unused xgpio_resume(struct device *dev)
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{
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struct xgpio_instance *gpio = dev_get_drvdata(dev);
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struct irq_data *data = irq_get_irq_data(gpio->irq);
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if (!data) {
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dev_dbg(dev, "IRQ not connected\n");
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return pm_runtime_force_resume(dev);
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}
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if (!irqd_is_wakeup_set(data))
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return pm_runtime_force_resume(dev);
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return 0;
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}
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static int __maybe_unused xgpio_runtime_suspend(struct device *dev)
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{
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struct xgpio_instance *gpio = dev_get_drvdata(dev);
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clk_disable(gpio->clk);
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return 0;
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}
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static int __maybe_unused xgpio_runtime_resume(struct device *dev)
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{
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struct xgpio_instance *gpio = dev_get_drvdata(dev);
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return clk_enable(gpio->clk);
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}
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static const struct dev_pm_ops xgpio_dev_pm_ops = {
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SET_SYSTEM_SLEEP_PM_OPS(xgpio_suspend, xgpio_resume)
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SET_RUNTIME_PM_OPS(xgpio_runtime_suspend,
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xgpio_runtime_resume, NULL)
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};
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/**
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* xgpio_irq_mask - Write the specified signal of the GPIO device.
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* @irq_data: per IRQ and chip data passed down to chip functions
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*/
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static void xgpio_irq_mask(struct irq_data *irq_data)
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{
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unsigned long flags;
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struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data);
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int irq_offset = irqd_to_hwirq(irq_data);
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int bit = xgpio_to_bit(chip, irq_offset);
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u32 mask = BIT(bit / 32), temp;
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spin_lock_irqsave(&chip->gpio_lock, flags);
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__clear_bit(bit, chip->enable);
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if (xgpio_get_value32(chip->enable, bit) == 0) {
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/* Disable per channel interrupt */
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temp = xgpio_readreg(chip->regs + XGPIO_IPIER_OFFSET);
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temp &= ~mask;
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xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, temp);
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}
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spin_unlock_irqrestore(&chip->gpio_lock, flags);
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gpiochip_disable_irq(&chip->gc, irq_offset);
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}
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/**
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* xgpio_irq_unmask - Write the specified signal of the GPIO device.
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* @irq_data: per IRQ and chip data passed down to chip functions
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*/
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static void xgpio_irq_unmask(struct irq_data *irq_data)
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{
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unsigned long flags;
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struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data);
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int irq_offset = irqd_to_hwirq(irq_data);
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int bit = xgpio_to_bit(chip, irq_offset);
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u32 old_enable = xgpio_get_value32(chip->enable, bit);
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u32 mask = BIT(bit / 32), val;
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gpiochip_enable_irq(&chip->gc, irq_offset);
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spin_lock_irqsave(&chip->gpio_lock, flags);
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__set_bit(bit, chip->enable);
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if (old_enable == 0) {
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/* Clear any existing per-channel interrupts */
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val = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET);
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val &= mask;
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xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, val);
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/* Update GPIO IRQ read data before enabling interrupt*/
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xgpio_read_ch(chip, XGPIO_DATA_OFFSET, bit, chip->last_irq_read);
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/* Enable per channel interrupt */
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val = xgpio_readreg(chip->regs + XGPIO_IPIER_OFFSET);
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val |= mask;
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xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, val);
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}
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spin_unlock_irqrestore(&chip->gpio_lock, flags);
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}
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/**
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* xgpio_set_irq_type - Write the specified signal of the GPIO device.
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* @irq_data: Per IRQ and chip data passed down to chip functions
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* @type: Interrupt type that is to be set for the gpio pin
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*
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* Return:
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* 0 if interrupt type is supported otherwise -EINVAL
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*/
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static int xgpio_set_irq_type(struct irq_data *irq_data, unsigned int type)
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{
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struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data);
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int irq_offset = irqd_to_hwirq(irq_data);
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int bit = xgpio_to_bit(chip, irq_offset);
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/*
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* The Xilinx GPIO hardware provides a single interrupt status
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* indication for any state change in a given GPIO channel (bank).
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* Therefore, only rising edge or falling edge triggers are
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* supported.
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*/
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switch (type & IRQ_TYPE_SENSE_MASK) {
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case IRQ_TYPE_EDGE_BOTH:
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__set_bit(bit, chip->rising_edge);
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__set_bit(bit, chip->falling_edge);
|
|
break;
|
|
case IRQ_TYPE_EDGE_RISING:
|
|
__set_bit(bit, chip->rising_edge);
|
|
__clear_bit(bit, chip->falling_edge);
|
|
break;
|
|
case IRQ_TYPE_EDGE_FALLING:
|
|
__clear_bit(bit, chip->rising_edge);
|
|
__set_bit(bit, chip->falling_edge);
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
irq_set_handler_locked(irq_data, handle_edge_irq);
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* xgpio_irqhandler - Gpio interrupt service routine
|
|
* @desc: Pointer to interrupt description
|
|
*/
|
|
static void xgpio_irqhandler(struct irq_desc *desc)
|
|
{
|
|
struct xgpio_instance *chip = irq_desc_get_handler_data(desc);
|
|
struct gpio_chip *gc = &chip->gc;
|
|
struct irq_chip *irqchip = irq_desc_get_chip(desc);
|
|
DECLARE_BITMAP(rising, 64);
|
|
DECLARE_BITMAP(falling, 64);
|
|
DECLARE_BITMAP(all, 64);
|
|
int irq_offset;
|
|
u32 status;
|
|
u32 bit;
|
|
|
|
status = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET);
|
|
xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, status);
|
|
|
|
chained_irq_enter(irqchip, desc);
|
|
|
|
spin_lock(&chip->gpio_lock);
|
|
|
|
xgpio_read_ch_all(chip, XGPIO_DATA_OFFSET, all);
|
|
|
|
bitmap_complement(rising, chip->last_irq_read, 64);
|
|
bitmap_and(rising, rising, all, 64);
|
|
bitmap_and(rising, rising, chip->enable, 64);
|
|
bitmap_and(rising, rising, chip->rising_edge, 64);
|
|
|
|
bitmap_complement(falling, all, 64);
|
|
bitmap_and(falling, falling, chip->last_irq_read, 64);
|
|
bitmap_and(falling, falling, chip->enable, 64);
|
|
bitmap_and(falling, falling, chip->falling_edge, 64);
|
|
|
|
bitmap_copy(chip->last_irq_read, all, 64);
|
|
bitmap_or(all, rising, falling, 64);
|
|
|
|
spin_unlock(&chip->gpio_lock);
|
|
|
|
dev_dbg(gc->parent, "IRQ rising %*pb falling %*pb\n", 64, rising, 64, falling);
|
|
|
|
for_each_set_bit(bit, all, 64) {
|
|
irq_offset = xgpio_from_bit(chip, bit);
|
|
generic_handle_domain_irq(gc->irq.domain, irq_offset);
|
|
}
|
|
|
|
chained_irq_exit(irqchip, desc);
|
|
}
|
|
|
|
static const struct irq_chip xgpio_irq_chip = {
|
|
.name = "gpio-xilinx",
|
|
.irq_ack = xgpio_irq_ack,
|
|
.irq_mask = xgpio_irq_mask,
|
|
.irq_unmask = xgpio_irq_unmask,
|
|
.irq_set_type = xgpio_set_irq_type,
|
|
.flags = IRQCHIP_IMMUTABLE,
|
|
GPIOCHIP_IRQ_RESOURCE_HELPERS,
|
|
};
|
|
|
|
/**
|
|
* xgpio_probe - Probe method for the GPIO device.
|
|
* @pdev: pointer to the platform device
|
|
*
|
|
* Return:
|
|
* It returns 0, if the driver is bound to the GPIO device, or
|
|
* a negative value if there is an error.
|
|
*/
|
|
static int xgpio_probe(struct platform_device *pdev)
|
|
{
|
|
struct xgpio_instance *chip;
|
|
int status = 0;
|
|
struct device_node *np = pdev->dev.of_node;
|
|
u32 is_dual = 0;
|
|
u32 width[2];
|
|
u32 state[2];
|
|
u32 dir[2];
|
|
struct gpio_irq_chip *girq;
|
|
u32 temp;
|
|
|
|
chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
|
|
if (!chip)
|
|
return -ENOMEM;
|
|
|
|
platform_set_drvdata(pdev, chip);
|
|
|
|
/* First, check if the device is dual-channel */
|
|
of_property_read_u32(np, "xlnx,is-dual", &is_dual);
|
|
|
|
/* Setup defaults */
|
|
memset32(width, 0, ARRAY_SIZE(width));
|
|
memset32(state, 0, ARRAY_SIZE(state));
|
|
memset32(dir, 0xFFFFFFFF, ARRAY_SIZE(dir));
|
|
|
|
/* Update GPIO state shadow register with default value */
|
|
of_property_read_u32(np, "xlnx,dout-default", &state[0]);
|
|
of_property_read_u32(np, "xlnx,dout-default-2", &state[1]);
|
|
|
|
bitmap_from_arr32(chip->state, state, 64);
|
|
|
|
/* Update GPIO direction shadow register with default value */
|
|
of_property_read_u32(np, "xlnx,tri-default", &dir[0]);
|
|
of_property_read_u32(np, "xlnx,tri-default-2", &dir[1]);
|
|
|
|
bitmap_from_arr32(chip->dir, dir, 64);
|
|
|
|
/*
|
|
* Check device node and parent device node for device width
|
|
* and assume default width of 32
|
|
*/
|
|
if (of_property_read_u32(np, "xlnx,gpio-width", &width[0]))
|
|
width[0] = 32;
|
|
|
|
if (width[0] > 32)
|
|
return -EINVAL;
|
|
|
|
if (is_dual && of_property_read_u32(np, "xlnx,gpio2-width", &width[1]))
|
|
width[1] = 32;
|
|
|
|
if (width[1] > 32)
|
|
return -EINVAL;
|
|
|
|
/* Setup software pin mapping */
|
|
bitmap_set(chip->sw_map, 0, width[0] + width[1]);
|
|
|
|
/* Setup hardware pin mapping */
|
|
bitmap_set(chip->hw_map, 0, width[0]);
|
|
bitmap_set(chip->hw_map, 32, width[1]);
|
|
|
|
spin_lock_init(&chip->gpio_lock);
|
|
|
|
chip->gc.base = -1;
|
|
chip->gc.ngpio = bitmap_weight(chip->hw_map, 64);
|
|
chip->gc.parent = &pdev->dev;
|
|
chip->gc.direction_input = xgpio_dir_in;
|
|
chip->gc.direction_output = xgpio_dir_out;
|
|
chip->gc.get = xgpio_get;
|
|
chip->gc.set = xgpio_set;
|
|
chip->gc.request = xgpio_request;
|
|
chip->gc.free = xgpio_free;
|
|
chip->gc.set_multiple = xgpio_set_multiple;
|
|
|
|
chip->gc.label = dev_name(&pdev->dev);
|
|
|
|
chip->regs = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(chip->regs)) {
|
|
dev_err(&pdev->dev, "failed to ioremap memory resource\n");
|
|
return PTR_ERR(chip->regs);
|
|
}
|
|
|
|
chip->clk = devm_clk_get_optional(&pdev->dev, NULL);
|
|
if (IS_ERR(chip->clk))
|
|
return dev_err_probe(&pdev->dev, PTR_ERR(chip->clk), "input clock not found.\n");
|
|
|
|
status = clk_prepare_enable(chip->clk);
|
|
if (status < 0) {
|
|
dev_err(&pdev->dev, "Failed to prepare clk\n");
|
|
return status;
|
|
}
|
|
pm_runtime_get_noresume(&pdev->dev);
|
|
pm_runtime_set_active(&pdev->dev);
|
|
pm_runtime_enable(&pdev->dev);
|
|
|
|
xgpio_save_regs(chip);
|
|
|
|
chip->irq = platform_get_irq_optional(pdev, 0);
|
|
if (chip->irq <= 0)
|
|
goto skip_irq;
|
|
|
|
/* Disable per-channel interrupts */
|
|
xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, 0);
|
|
/* Clear any existing per-channel interrupts */
|
|
temp = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET);
|
|
xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, temp);
|
|
/* Enable global interrupts */
|
|
xgpio_writereg(chip->regs + XGPIO_GIER_OFFSET, XGPIO_GIER_IE);
|
|
|
|
girq = &chip->gc.irq;
|
|
gpio_irq_chip_set_chip(girq, &xgpio_irq_chip);
|
|
girq->parent_handler = xgpio_irqhandler;
|
|
girq->num_parents = 1;
|
|
girq->parents = devm_kcalloc(&pdev->dev, 1,
|
|
sizeof(*girq->parents),
|
|
GFP_KERNEL);
|
|
if (!girq->parents) {
|
|
status = -ENOMEM;
|
|
goto err_pm_put;
|
|
}
|
|
girq->parents[0] = chip->irq;
|
|
girq->default_type = IRQ_TYPE_NONE;
|
|
girq->handler = handle_bad_irq;
|
|
|
|
skip_irq:
|
|
status = devm_gpiochip_add_data(&pdev->dev, &chip->gc, chip);
|
|
if (status) {
|
|
dev_err(&pdev->dev, "failed to add GPIO chip\n");
|
|
goto err_pm_put;
|
|
}
|
|
|
|
pm_runtime_put(&pdev->dev);
|
|
return 0;
|
|
|
|
err_pm_put:
|
|
pm_runtime_disable(&pdev->dev);
|
|
pm_runtime_put_noidle(&pdev->dev);
|
|
clk_disable_unprepare(chip->clk);
|
|
return status;
|
|
}
|
|
|
|
static const struct of_device_id xgpio_of_match[] = {
|
|
{ .compatible = "xlnx,xps-gpio-1.00.a", },
|
|
{ /* end of list */ },
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, xgpio_of_match);
|
|
|
|
static struct platform_driver xgpio_plat_driver = {
|
|
.probe = xgpio_probe,
|
|
.remove = xgpio_remove,
|
|
.driver = {
|
|
.name = "gpio-xilinx",
|
|
.of_match_table = xgpio_of_match,
|
|
.pm = &xgpio_dev_pm_ops,
|
|
},
|
|
};
|
|
|
|
static int __init xgpio_init(void)
|
|
{
|
|
return platform_driver_register(&xgpio_plat_driver);
|
|
}
|
|
|
|
subsys_initcall(xgpio_init);
|
|
|
|
static void __exit xgpio_exit(void)
|
|
{
|
|
platform_driver_unregister(&xgpio_plat_driver);
|
|
}
|
|
module_exit(xgpio_exit);
|
|
|
|
MODULE_AUTHOR("Xilinx, Inc.");
|
|
MODULE_DESCRIPTION("Xilinx GPIO driver");
|
|
MODULE_LICENSE("GPL");
|