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0969001569
Microchip's pci1xxxx is an unmanaged PCIe3.1a switch for consumer, industrial, and automotive applications. This switch integrates OTP and EEPROM to enable customization of the part in the field. This patch adds support to read and write into PCI1XXXX OTP via NVMEM sysfs. Signed-off-by: Kumaravel Thiagarajan <kumaravel.thiagarajan@microchip.com> Co-developed-by: Tharun Kumar P <tharunkumar.pasumarthi@microchip.com> Signed-off-by: Tharun Kumar P <tharunkumar.pasumarthi@microchip.com> Co-developed-by: Vaibhaav Ram T.L <vaibhaavram.tl@microchip.com> Signed-off-by: Vaibhaav Ram T.L <vaibhaavram.tl@microchip.com> Link: https://lore.kernel.org/r/20230620143520.858-2-vaibhaavram.tl@microchip.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
14 lines
572 B
Text
14 lines
572 B
Text
config GP_PCI1XXXX
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tristate "Microchip PCI1XXXX PCIe to GPIO Expander + OTP/EEPROM manager"
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depends on PCI
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depends on GPIOLIB
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depends on NVMEM_SYSFS
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select GPIOLIB_IRQCHIP
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select AUXILIARY_BUS
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help
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PCI1XXXX is a PCIe GEN 3 switch with one of the endpoints having
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multiple functions and one of the functions is a GPIO controller
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which also has registers to interface with the OTP and EEPROM.
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Select yes, no or module here to include or exclude the driver
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for the GPIO function.
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